Good morning, everybody. Thank you for joining us today. I'd like to, on behalf of the Board of Management of ASML, welcome you here, and thank you for those people in the room, and good afternoon and good evening for those listening on the webcast. Also, I'd like to wish you a happy Halloween. It's unfortunate those people that aren't in the room don't get to see my costume, but I spent a lot of time and energy on it, and it got raving reviews. You'll have to ask about it, those people on the webcast. Anyway, let's get started here. Mobile devices off, please. You probably discovered already that you have power underneath your tables if you need that. Let me do a little bit of introduction. Again, in the Halloween theme, don't be afraid. We're going to talk technical. We can't help it.
It's what we do. It's how we create value and opportunity for the world, including you guys. Bear with us. Three things to remember, simply, we're tasked with the objective of creating a quality image for our customers with these very complicated machines. We have to make sure that we place them very accurately, one against the next. Once we do those two things and do it very well and control those patterns and those pattern placements, customers want us to do it as fast as we can. That's our challenge. That's all you need to know. We've kind of branded this thing as Small Talk. Some people were bothered by that within ASML because they thought that was kind of a negative thing, that's gossip and chatter and so forth. It really makes sense to us because that's what we'll talk about.
We're going to talk about nanometers, and a nanometer, just so you know, is a billionth of a meter. Peter's going to talk about our DNA. DNA is two nanometers wide. Another example, your hair grows at eight nanometers per second, your grass grows at 33 nanometers per second, and a red blood cell is 7,500 nanometers wide. It just gives you a sense of how small we're talking. I hope you'll appreciate that when you think of the complexity of these tools and the success we've had in meeting our customers' requirements in that regard. Just by way of an agenda review, I'll be followed by Peter Wennink. He'll talk about creating value for our stakeholders. Martin van den Brink will talk about litho today, litho tomorrow, a bit of our roadmaps, et cetera.
Hans will talk about EUV program and the status of that, followed by Christophe, who will talk about our holistic lithography business. Wolfgang will bring it all together and give you an update on our business model. Peter will close up. We will have a Q&A session for about 30 minutes, and then after that, we'll adjourn, and you're free to have some snacks in the other room again, and we can chitchat a bit more about our business. I think that covers it. Before I introduce Peter, I want to play just a short kind of introductory video. I hope you'll bear with us on that, and then Peter will come to the stage. Last thing is this. It is Halloween, and I'm going to torture you. I'm going to read this whole thing. Just kidding.
Before we begin, I would like to caution listeners that today's comments made by management during the event will include forward-looking statements within the meaning of the federal securities laws. These forward-looking statements involve material risks and uncertainties. For a discussion of these risk factors, I encourage you to review the safe harbor statement you see here. They're contained in each of today's presentations, and you can find them on our website, and in ASML's annual report on Form 20-F and other documents that we file with the Securities and Exchange Commission. With that, a short video, and then you'll see Peter come up here on stage. Thanks.
Few inventions have transformed the world as dramatically as the computer chip. In our world today, chips are everywhere. This progress in technology is fueled by the semiconductor industry's drive to make chips smaller, more powerful, and cheaper year after year. ASML makes the machines that are used to manufacture these chips. All of the world's top chip makers are our customers. Chances are that every day you use a device that was partly made on our lithography machines. The lithography machines that we make are essentially a projection system. Laser light is projected through a blueprint or mask of the pattern that will be printed. Optics focus the pattern onto a silicon wafer with light-sensitive chemical coating. When the unexposed parts are etched away, the pattern is revealed. This process is repeated to create billions of tiny structures on one chip.
Structures are placed on top of each other with an accuracy of just two nanometers, while the wafer accelerates as fast as a jet fighter. That's cutting-edge technology, considering the diameter of a human hair is 100,000 nanometers. It sounds complex, and trust us, it is. It takes the best and brightest minds. We also rely on a global ecosystem of high-tech suppliers, strategic partners, and research institutes. We call this open innovation. In our clean rooms, we integrate the 50,000 parts that make up a single machine before it is shipped out to a customer's semiconductor fab. Every single day, in customer fabs around the world, our machines help make chips that drive the world forward. We're proud that our creative
Okay. That was a great video, Craig. First time I've seen it. Before I start my presentation, I'd like to have a warm welcome to our Chairman of the Supervisory Board, Gerard Kleisterlee, who's sitting in the back, who is making sure that we say the right things. No, I'm just kidding. He's here to also, if you have questions, he is here, and we're very happy to have him here. Good. Craig, how does this work? Green button. Good. This is it. This work? Yes, it does. What I'm going to talk about, Craig actually said it. I think it's particularly important that we understand who we are and who we work for. I think our DNA, when we talk about our DNA, is really the complex set of value that we will create, not only for you as our shareholders, but also for our customers.
Very important, our people, and also extremely important in the system that we work in. It was mentioned in the video, open innovation is only possible when you have a very close connection to our supply chain. It's extremely important. It's all focused on-- it's a small difference in this particular statement, because people that may remember this statement from our presentation two years ago could have noticed a significant difference in the sense that we say we are delivering superior integrated patterning solutions today. We used to say imaging solutions. Now, imaging is just a subset of patterning. Over the last two years, it's become apparent, hopefully also to you, that this company doesn't only image. We don't only make the camera. That is what we are.
In the presentation that you're going to see going forward, it's going to be a very important element. Christophe is going to talk about holistic lithography. Martin is going to show that our product strategy is really based on this tripod, which is the EUV. That is the lithography scanner. It's the metrology systems that we have, and it's the computational lithography competence binding it all together. This is who we are. We do this for an industry, and this industry is not only our customers. We need to realize that this is a large ecosystem with a massive profitability. It's not only financial capital there. There's massive amounts of human capital. That industry is reinventing itself continuously. If we would have done this presentation a year and a half ago, a lot of questions would be on, what's the next killer application?
There is a slew of new applications coming. Because our customers keep driving innovation. We'll definitely see this in new connected devices, and I'll talk about it a bit later. We do this for our customers, relentlessly focusing on innovation, because they do feel that the innovation that they provide will create affordable electronics. Their technology roadmaps are continuously supporting this. When we talk to our customers, we talk about roadmaps that go way into the next decade. It also means that our products are focused and are matched to those roadmaps. Clearly, our products, with what kind of products do we do this? I think it is definitely EUV, but the workhorse of the industry is Deep UV. The glue that makes it all work together to get together a pattern fidelity on those wafers is holistic lithography.
EUV will also take us way into the next decade. Hans will talk about this. Martin will also talk about this. In the end, the market opportunities, what does that mean to us? We can comfortably confirm our 2020 target of €10 billion and more than, I would say, €8 of earnings. That will also be helped with the acquisition of HMI, which we're at the verge of closing as we received all the necessary approvals. The EUR 10 billion that we set two years ago is actually going to be higher with the HMI acquisition, and Wolfgang is going to talk about that. 2020 is not where it all ends, as I will go into some detail.
We go through our simulation, we take the customer roadmaps, we take our product portfolio, we take a certain assumption on the growth of the end markets, then you will see that there is a significant growth opportunity beyond 2020, and I'll touch on that in our presentation. This is quick. Basically, on those four stakeholders, customers, we added productivity. We did some decent capital returns to our shareholders. We almost tripled the number of highly paid and highly educated people in the company. We kept fueling a lot of money into the supply chain. I think this is an important slide. Why I think it is important, because if you look at the earnings capability of the ecosystem that we are driving, this little blue line on top is the semiconductor equipment industry.
They are providing our customers with the solutions to make those cost-effective chips. These semi designs can actually be made and can be worked into hardware that actually fuels all the service companies, so the likes of the Googles and the Microsofts and the Oracles of this world. That ecosystem has an earnings power, EBIT, of close to $300 billion. That's a massive amount of financial and human capital. Why is that important? Because yes, people are always concerned about Moore's Law and the end of Moore's Law and Martin will talk about this quite clearly. It is this enormous human capital power and financial power that will drive this industry. There's so much value there. What will it drive? We look at this chart, you see at the left top-hand side, the things that we know today.
The mobile and PC market is maturing. Yes, there is going to be low single-digit expected growth on smartphones. However, the IC content of those phones is going up continuously. We look at the roadmaps of our customers' processing power and also the power usage, those are all elements that go to the next phases, where they need advanced litho. IC content in the smartphone market is going up still significantly. However, what will it fuel? It will be the smartphones and connected device will be part of a much bigger system, and we call it Internet of Things. In fact, it's all about connectivity. It's about connected devices. Whether it's machine to machine or whether it's in your car, whether it's automotive, this is going to happen. It has to be channeled through the cloud.
We look at the current forecast of unit shipments in terms of servers, quite significant double-digit growth of number of units. When you look at the content of those servers, very high power microprocessors in there and a lot of storage. Martin will show you something about storage and about the very heterogeneous landscape when you think about memory. Memory 10, 15 years ago was simple. It was DRAM and APC. It's not that simple anymore. It's much, much more complex. That will drive connected devices. One I would like to highlight, cars. I asked this CEO of one of our major customers, he actually talked to us a couple of months ago, and he said, "Our car manufacturer customers are basically customers that are two to three generations behind the most advanced customer that we have." It was a foundry customer.
Within 5 years," and we talk about 5 nanometer, "they're going to be the most advanced customer set that we have. When we look at their designs and the requirements, it's by far the most." He said, "Well, the world sells about 110 million-120 million cars per year, 1.3 billion smartphones. The high power IC content is 10 times higher in a car than in a smartphone." It's going to be a significant growth market. Yes, those markets will be there. What does that mean for us? It means for us and our customers, that there need to be more wafers. When you look at this chart, it has three elements. It's a logic segment. It's what we call the performance memory segment, let's say DRAM, and it's storage.
It's storage memory, which is NAND, storage class memory, which could be XPoint, ReRAM. Those three segments are there. When you look at the wafer growth that we expect till 2025, it's about 9% compound annual growth in logic. The first step will still be, till 2020, will still be smartphones. There's still a very significant drive of higher and more complex and powerful IC content in the smartphone. It will drive this Internet of Things. After that, it will be IoT and other. Other will be connected devices. It will be machine to machine, like I said, human to machine to human, and vice versa, and there's going to be a significant growth in that area. The wafer growth will be driven by that particular part of the market.
When you look at memory, performance memory, DRAM, will also definitely benefit from the server market, the increase of the server market, but also from IoT and from the connected devices. They all need performance memory in there. Storage, storage will be driven by the cloud. It will be very much driven by the big server parks and the massive amount of storage demand that will be there. This is all the result of why we come to these numbers. This is the result of the roadmaps of our customers. A certain assumption on growth rates, as you see here, bit demand for performance memory, 25%, and for storage memory, around 40%. You get to these required extra wafers out. What about litho in those extra wafers?
When we look at the litho intensity in those three segments, logic, when we were at 32 nanometer, was about 17%, and when we go to 5 nanometers, which is about five, six years from now, it will be over 30%. It's not strange because we'll be driven by EUV, and we'll be driven by high-end DUV, and we'll also be driven by computational lithography, holistic lithography. In performance memory, once we go to 1X DRAM, and that's not that far away, we'll be about 27% of a greenfield fab. This is on a greenfield fab. You build a new fab. We go back to the previous slide. We need more wafers. We need to build a new fab. This is the resulting litho intensity over time. Look at storage.
Storage, it's a bit more complex because you have planar, you have 3D NAND, and you have the storage class memory, which is CrossPoint, ReRAM, PCRAM. Very clearly that we will probably not see a planar beyond 18 nm DRAM, 16 nm DRAM. First signs we have, it will be EUV. When we go to 3D NAND, 3D NAND will have a litho intensity in a greenfield fab about equal to where we are in DRAM today. When we go to the storage class memory, which will be scalable memory in three dimensions, in x and y direction and in the z direction, you can see quite a significant increase in litho intensity. Which will be, by the way, by the end of the decade, going into the next decade, early next decade. Then it will be about the same level of intensity as in performance memory.
The opportunities. We have 2 types of opportunities. We always talk about systems, and we talk about our service revenue, and installed base services, which is becoming more and more important. If we translate the wafer capacity and the need for advanced litho for the next generations, and which is translated into this litho intensity, then we can do the calculations and we see a litho market by 2020 of about EUR 10 billion for systems, and over EUR 15 billion by 2025. As driven by EUV. Next to that, what we're also seeing over the last couple of years is the focus that our customers have on capital efficiency and the use of their installed base.
They have a very high capital installed base, and that gives us a lot of opportunity to actually bring the current installed base partially to the next level, to the next node level. That gives us a lot of opportunity. We see that business growing to over EUR 5 billion over the next 8 to 10 years. Around EUR 3 billion by the end of the decade. Significant growth opportunities driven by the roadmaps of our customers, the need for more wafers and higher litho intensity. Going in there, little bit more detail. What are our assumptions there for the systems market? We do assume that we will deliver the full roadmap. There's no doubt in our mind that customers need the full roadmap. There's no doubt in our mind that we can execute, and that customers will continue to shrink.
They will execute on that shrink roadmap because the cost advantages, the cost per transistor advantages are so compelling. We do assume a 3-year roadmap. As you may remember, two years ago, we said we have this 2-year roadmap or a 3-year roadmap. I think we all agree that the complexity with which customers are currently executing their roadmaps drives to a 3-year cadence. There's a 3-year cadence in there. We have used moderate growth assumptions on the existing application markets. There are many research institutes out there. You can have higher numbers, you can have lower numbers. Wolfgang will talk about some of those in his presentation. All in all, we see a potential of over EUR 15 billion in 2025 and around EUR 10 billion on systems in 2020. That equates to about a 9% compound annual growth rate.
Well, that all sounds great. The customers buy a lot more litho and litho intensity goes up. What does that mean to our customers? Is this still affordable? These are slides that are not ours. This is a customer slide, the left one, that actually shows you that the cost per function is still going down. Actually, you can see an acceleration around the 10 to seven nanometers. Also when we plot five, it's the same thing. It stays at that line, or you could even argue it is lower than the cost. It's on a logarithmic scale. It's even sharper down than a straight line down. All the translation of these costs into what counts for the customer, which is the cost per transistor, actually shows you that everything that we assume supports this.
When the cost per transistor keeps reducing, customers will shrink. They will buy those litho tools, and they will make those devices that go into the end markets that I talked about. This will happen. There's another nice chart that was put out that basically says, can we still afford it? I think it was quite insightful. The non-recurring engineering, the R&D cost for every new node historically is 10% higher with every node. Well, the break-even point is 190%. You could increase your R&D node to 190%, and you would be break even. Well, we are way lower than that. It actually provides massive value to keep going down and to keep shrinking. Okay, installed base.
Like I said, it's inevitable that customers will look at the capital efficiency of what they have bought over time, and I think it provides a fantastic opportunity for us. It not only provides an opportunity because we can upgrade the existing installed base to the next node, which are, when you think about system upgrades, those are not cheap. The most expensive upgrades momentarily are around EUR 30 million apiece. It also provides us a basis for thinking about a service model, which is different than what we do today. Today, effectively, we sell misery, where tool breaks down, where the wheel comes off, we go to the customer and say, "Well, we put the wheel back on and here's the bill." In fact, we are going to, we do this with EUV, we go to sales per wafer.
Basically, we charge you with a service charge per wafer. You give us the challenge to make money with it. It's a bit like what we do with Cymer, where we sell the service model for the DUV lasers as an on-pulse model. We pay per pulse, they pay per billion pulses. Per billion pulses, we charge you. Here we just charge you per wafer. Which we all believe is one is much more predictable what our service revenue is going to be, and you get more focus on our internal cost. I think it's a good model. Next to that, like I said, is the performance upgrades, which provide significant value for our customers, but also significant business opportunity for us. Also there, we believe that the compound annual growth rate will be around the 10%, the 9% to 10% in our area.
This brings this install base business to over EUR 5 billion in 2025. We keep growing. It all sounds great. Are there no challenges? I think there are challenges. I think there are challenges at three levels. Customers. Main challenge for our customers is cost. Cost and quality. Cost is, in absolute terms, cost is going up. We need to manage that cost together with our customers to be able to keep reducing the cost per transistor. That is more relevant and more in the area of focus with our customers than ever before. Of course, there are concerns, which I think we're going to talk about, on the speed of EUV industrialization. As Hans will clearly show you, EUV works, but it's about the speed of industrialization. Customers need it fast.
They need it before the end of the decade in their factories to do mass production. This is what we talk with customers. These are the challenges, Hans will go into detail. Suppliers. I think if the technology becomes more complex, then also the complexity is reflected in the supply chain. This means that we need bigger suppliers that can deal with the investments, that can deal with the inherent risks. It also means that those suppliers need to be able to invest timely, not low scale, but large scale, so we can manage the lead time. In EUV, for instance, the lead time is two years, which is too long. It needs to go down to 12 months. Our plan is to bring it down to 12 months by the end of the decade.
That is a challenge that we have in the supply chain. From a competitive point of view, the dry litho market, which is the lower end of our market, we have competition there. That competition is increasing because they're not expanding at the leading edge. We have to make sure that the very good market position we have in immersion stays there, Martin will talk about this. We have a very convincing dry and immersion roadmap. There's also, you could say, blurring domains. Life used to be simple. You had metrology companies and you have litho companies and you have etch companies and you have deposition companies, but it all blends a bit into what we call patterning. This is also what we need to be carefully considering.
Our challenge is to remain competitive in DUV, to bring EUV to high volume industrialization, and the trick up the sleeve is holistic lithography and integrate that into our product offering. In summary, our DNA is focused on creating value for our stakeholders by providing superior integrated patterning solutions, which definitely includes metrology. We do this in an industry that has the power, the intellectual, the human capital, and the financial power to drive this industry and to come up with continued innovations because they can keep reducing cost per transistor, which drives their technology roadmaps, and is also a clear drive for innovations. This has a direct effect on our own systems.
We keep investing in our core product, DUV, in the trick up the sleeve of the holistic lithography program, and of course, in EUV, because EUV will drive lithography and the shrink of our customers in the next decade or the next 10 to 15 years. The opportunity is clear then. I think the opportunity is, yes, we comfortably confirm or reconfirm our EUR 10 billion target for 2020, excluding HMI, which brings us an EPS of over EUR eight per share. Beyond that, I think is an important message, we see significant growth opportunities towards 2025, basically at growth rates very similar to what we see today. With that, I would like to close off and give the floor to Martin to talk about litho today and litho tomorrow. And beware of the slide that Craig put up. This is Halloween. Don't be afraid of technology. Thanks. Thank you.
Thank you very much, Peter.
I'm going to start with some light slides. Before I do so, this is the overview of the presentation. I'm going to talk about industry trends at large. I'm going to try to focus in what it means for our customers, and how it will determine our strategic priorities. I will show you that we can mirror that with a significant specific roadmap. This is a slide, which I said is a bit light. Slide is from Ray Kurzweil. He has a few controversial positions. This is what I don't like to elaborate on much. He did a nice job of plotting for the last 100 years how calculation speed progressed per EUR 100,000 spent. When Moore's Law was coming into play in 1964, you could see that the world was already on doubling speed for 65 years.
As you see, mechanical computers, relay computers, you have tubes, you have transistors. You see all of this doubling speed come with disruptions in technology, but it never stopped. I could move on and say, when I joined ASML in 1984, and I was looking back how much progress being made for 84 years. I said how possibly we could add significant value given the enormous progress already being made. Today, we are here, I'm looking back 30 years and said, "Well, we're able to continue for 30 years, but God knows how we do the next 30 years." Some of us say, "We have made so much progress in the past, we are likely going to redo this." Well, if I start dreaming a bit from today, you could argue, I will not argue we'll continue for 30 years. It will go forever.
The likelihood that we would fall off the cliff based on this graph is suggested. There's no science, there's nothing there to say this has to be there. As long we have new ideas, there's no reason to believe that Moore's Law will stop. If you put those last 20 years into a bit more detail, I just copied here a slide of John Kelly from IBM, how calculation speed and overall system performance will increase. There are a substantial amount of ideas to keep on going, I would like to claim if we're doing this for 100 years, why would it stop the next five years? I would say it will not stop as long as a significant amount of people keep on seeing that improving the calculation speed helps. What would be the customer of all this?
This has been said by many, I could be elaborating on this as a non-expert on applications. I'd like to limit myself that, as Peter already summarized just a moment ago, for 50 billion connected things by the end of this decennium, you will need to have devices who collect the data, which is predominantly mainstream, relatively low-tech device because cost is important. The data need to be stored, which will create a huge demand for data storage, once you have the data stored, you have to find ways to structure the data, that leads to massive calculation power needs. Every device, everything will connect it. That's what the overall trend is. Scaling was, of course, in the past an exclusive feature for geometrical scaling.
What you see lately, we see that there are various scaling engines, this is a slide I enriched based on a slide presented by Luc Van den hove from imec. Where you see on the left top side, the way we do traditional shrink. On the right-hand side, you see how circuit scaling by integrating different devices, single packaging, improve the architecture, you also add substantial amount of calculation speed. On the left top, something we have been living for planar transistors for 30, 50 years. We're now seeing FinFETs, we're seeing a FinFET being progressing into nanowires and vertical transistors. I added recently what I call architecture scaling.
This is particularly visible in the memory market, where the world was about DRAM and almost no SSD and hard disk drive, where the future will be dominated by all kind of different solid-state devices, including new devices, which are cheaper and faster. To give this a bit more meat, this is the logic evolution. Until 2010 or so, we had planar transistors, where Intel introduced a 20 nanometer FinFET. What you see in the bottom left graph, that the switching threshold, even from FinFET, goes up, which means it's more difficult to switch. Alternatives are researched, the right-hand side you see that nanowire has been published by imec, is able to reduce the threshold again. Likely we'll have another evolution of a complete vertical nanowire moving forward.
This has somewhat more impact on process technology. I did of course, include the recent nanowire results of Berkeley, suggesting that from a technology point of view, there is not much reason to believe that scaling technology-wise will stop. When you go to memory, I would claim the revolution is even higher. I have been at memory suppliers as recently as last week. This picture is for some threatening, but some also a major opportunity. This shows that the hard disk drive, which is on the left side. The two axes are cost horizontal per gigabit and vertically the access time. This is the map of memory. On the low cost, high access time, slow memory is hard disk drive. They are losing it as we speak from NAND. This is why the logic of the merger between Western Digital and SanDisk is based on.
You see on the right-hand side, the traditional memory, working memory, DRAM and SRAM, where we have a lot of fast memory. You see a major time gap and cost gap between the hard disk NAND cost and speed versus the DRAM, SRAM. People looking already for many years to storage class memory, where recently Intel and Micron published their Crosspoint. From a technology point of view, you see that the current move from NAND is going from 2D to 3D, where the scaling is not done through cost but adding more layers, which we call litho-intensive, or not litho-intensive. We do on a single litho, you do many layers and try to reduce the cost per bit by increasing the amount of bits. When it comes to Crosspoint, you still see a bigger need for scaling things down.
You will have a limited amount of layers because they are more expensive, but the idea is that over time it has the opportunity to be cost competitive with NAND and certainly with DRAM. Finally, DRAM is already in a difficult place for some time. Shrinking DRAM moving forward is becoming an issue, as well as the geometry of NAND. You see this now coming clearer in the next slide. This is a recent slide from Micron, where you see in the vertical axis the relative data volume, right. Horizontal, the years. You see how the semiconductor content of it, SSD and DRAM, is increasing over time and likely will reduce the need of the high-end hard disk drives very quickly. Where you see on the right-hand side also of NAND and DRAM, Crosspoint coming in some major way.
I think in five years beyond this, we will likely see almost no hard disk and the thing will be completely driven by semiconductors, driving our value in terms of lithography. To explain you how shrink moves, I had to get a bit of a complicated slide as I see here, where you like to create this layout on the right-hand side. You do this by getting a very coarse image, in this case litho, which has double the pitch. You then you start deposits phases. You are going to etch this in two steps. All of a sudden, you have double the density. They call it pitch doubling. Once you have this pattern, you have to create a circuitry where you have to cut these lines. You have to go on with a cut mask.
The cut mask, you see you can do that in 2 phases. In order to do the density of cuts, you need to use it in 2 steps, in litho one and one etch, and the litho two and another etch. That is now the final result. As you can tell, where you in the past needed to have a single exposure and a single etch, you now have multiple exposures and multiple etch steps to do the job. For litho, you see that if you look into this node evolution, you see that this end-to-end cut is not a piece of cake. First of all, you have a certain uncertainty of your cut defined by CD uniformity error and overlay error. It can also cut, can be in the wrong place. You can at no single case cut into the next line.
That combination of CD and overlay, we call etch placement. If you start shrinking this device, so you have multiple cuts on different places, then you start shrinking the device. You can see that if you do nothing on your cut, you will ruin the whole patterning. Even with double patterning, you have to be more sophisticated. Your cut, you have to make the cut smaller by making the CD smaller. You could do it by overexposing. You also need to reduce the overlay, in order to get an overall etch placement improvement. Even if 193 will not improve their half pitch performance, we'll have major innovations in CD performance as well as an overlay in order to allow the shrink to continue.
That's why we say, if we do single exposure, which of course is the single exposure cut, is the most attractive way of doing it. A litho cut in multiple exposures can be done, but it's very costly. It's challenging also for the litho. That means we're not losing out on multiple cut. In fact, multiple cuts requires more litho. Equally difficult or even sometimes more difficult because of the etch placement complexity. For the customer, this is a way more complicated process, both from a cycle time point of view or from a cost. Hence, this overall roadmap for our customers. You see here logic, performance memory, storage class memory, storage memory. You see the storage memory, mainly the 2D integration, 2D shrink stops around 40, 50 nanometer and everything is now about 3D NAND. 3D NAND density in horizontal sense will likely not improve.
They will only scale vertically. The shrink is mainly due on the geometric shrink is normally logic and performance memory, storage class memory, where we see logic, given the previous animation, is the most challenging. Followed by DRAM, which will slow down a bit the shrink rate, and potentially that CrossPoint-type devices will take over the scaling in memory moving forward. That brings me to the 4 major priorities I'd like to highlight in the next few slides. For ASML, this means we need to get forward with industrialization of EUV. We will have a major impact on cost of our customers, which will be, in our view, the best guarantee of Moore's Law to continue. However, the cost of EUV is such, it will not substantially impact the amount of volumes for DUV for some time to come.
We'll see substantial mix and match between EUV and DUV coming. DUV remains to be very important. That means that holistic litho continues to be important because it has to connect both the litho with the process and going into pattern fidelity and if possible, pattern fidelity control. We are obligated, being a little company, not stopping at what we have today and also share with you and our customers our future vision how to shrink, which is EUV extension. This is, in short, the EUV insertion opportunity. You see that for logic, the litho etch three times would be blown up to four at 7 nanometer. There's an increasing need of replacing the multiple-pass argon fluoride with EUV single exposure, which likely continues to at least 5 nanometer.
You see for the 7 and 5, logic will be a major drive of EUV introduction. Since DM is a bit more conservative, they will first wait the logic guys to reduce the cost over time. They will also slowly, over time, implement EUV. I could have elaborated multiple slides on EUV. Hans will do that. I'd like to summarize the status in one thing. You will see that in itself, other than infrastructure challenges, the performance of EUV is almost not challenged. I skip all that. This is the major challenge on EUV. Yes, we do three days average of 1,500 wafers per day, as reported by TSMC.
Last week, [Brett Turcot] was designing a graph. It shows the daily uptime, where you see that this is a consistency EUV is not as good as we wanted. Although overall, you average out these downtime periods. The overall improvement of uptime is still significant. It's that balance will determine the aggression and the speed at which we're able to roll out EUV. Overall, the overall cost reduction of EUV is substantial. We expect around the sub 5 nanometer node of the sub 7 nanometer node, this 5 nanometer, around 30% cost. It's about the same litho cost. The cost reduction is in particular the non-litho CapEx. If you look to the productivity, we are closing in or have to reach our targets set out earlier this year for 2016, 1,500 wafers per day and 80%.
You see on the right-hand side some of the customer comments saying they really like to implement this EUV starting at 7 nanometer. With that, I'd like to move to DUV. DUV today is our major workhorse. We have to make sure that we are creating what I'm saying is the perfect machine. Peter already said that because of our technology drive, we are known as the Rolls-Royce supplier of litho. The amount of innovation going on in the machine sometimes hampers to get to the perfect uptime and support of our customers. We have to really focus on making these DUV systems as cost-effective for our customers as we can. Focus ourselves more on quality. The overall roadmap is given here. You see here is a metric of wafers per hour, which is mainly more or less cost for our customers.
Vertically, you see the overlay going down to bleeding numbers of 2 nanometers on product overlay. You see the various product models. The key of this is that we do like to reduce cost of our customers by allowing them to upgrade all of those machines to the latest model without forcing them to install a complete new machine. If you look to the improvements of the next generation machine being shipped around next year, you see here major innovations. All of them are focusing on improving the overlay and only a few on imaging, like the projection lens and the wafer table improvements. Overall, you see a huge, and also the leveling, a huge focus on the overlay.
I'd like to highlight 2 elements, which is the alignment sensor improvement and the level sensor improvement, both are focusing not on sheer accuracy, but mainly on the, how you call it, the robustness for different process layer. Here you see a graph of simulated alignment error. Remember, we don't have complex processing tools in effect, so we have to simulate them. This be simulated out of 30 different process stacks. You see the overlay today can vary up to a 0.5 nanometer, 5 nanometer. By improving our sensors, which I will just flip you over a bit, we see we can substantially reduce the excursions and the process robustness. We have simulated partly by using our existing sensor and manipulate the system to mimic the new sensor.
We see here almost a cut of a factor of 2 in some of the measured overlay of our customers. These are overlay on very complicated stacks. Similarly, on focus. You see on the left-hand side our focus system, which is very simple. You shine an amount of light on the wafer, you look to the reflective light position, the gravity point of the reflective light determines the focus position. However, interaction of that light with the process stacks confuses the focus position. We try to reduce that by having a closer angle to the wafer, so we have more like throwing a stone on a piece of water. You have to do that in a way it bounces off, the same for light. You shorten the wavelength to increase the absorption and reduce the interaction with the process stacks.
By doing so, we have shown here on 7 different customer process layers, a substantial improvement of our focus accuracy. These are the kind of improvements which are highly in need of our DUV product line and will be also mitigate over time into EUV. Finally, it's our dry roadmap slide. You see it mimics a bit the high-end line where the numbers are slightly different. Everything we do, we'll try to port in our mainstream products to continue to increase their productivity and the overlay also through upgrades. With that, I'd like to continue with our third priority, named holistic litho. Holistic litho has 6 competencies. I would say 3 competencies and 3 products of value, which is the litho piece, number 1. I talked about it in the previous section. We'll continue to talk about it in EUV section. It's about metrology. It's about computational litho.
It is how you fill the triangle with products, process window enhancement, we talked about in the past. Process window control, which we'll talk about shortly, and process window detection. We have to excel in all three areas to keep this thing going, hence the addition of HMI, where Christophe will talk about. This is for many, perhaps a difficult graph, but this is what we see as a product for metrology. You're looking to a top-down multilayer DRAM feature where you see the underlying two stacks overlays on the way, you see becoming asymmetric depending on the overlay going to left or right. Today, our metrology system, YieldStar, is the only tool who can look directly on product, on customer structures to potential asymmetry to that overlay, and even is able to do that even more accurately than CD-SEM.
These kind of capability will determine how much we can improve our overall system overlay to the process, because it's very difficult to measure through in process these anomalies of overlay. This is also a bit complicated. This is a negative tone resist progress. Customers move from positive tone to negative tone resist for the simple reason that the contrast is improving by reversing the contrast of the resist. However, where they previously washed away the exposed area, today the exposed area remains, and exposed areas, exposed to photons of short wavelengths are stressed, and the mechanical stress was not part of the resist model.
Today we are the only vendor today in providing this level of accuracy where we include the mechanical component next to the optical modeling, allowing you to do a much better OPC correction, where the OPC correction is not only calibrated out like for other models, but now you also see if you deviate the layout, the whole modeling remains robust. The holistic way of working is best being shown to this. This is what you see in a fab. You see left-hand side, a stepper, right-hand side, a track. You see our metrology system built in a track. It measure focus and overlay. It starts going through some computational calculations, start controlling the stepper. By doing so, you see about a nanometer gain on the overlay. Moving forward, we see a roadmap where this could be more sophisticated.
First of all, we're going to add as well the scanner internal metrology system. As I showed you a moment ago, we have improved the process robustness and therefore the reliability of those measurements. Right-hand side, we start adding the E-beam system through HMI, where we're going to teach this HMI system to look at certain places, but also calibrate our models moving forward. That leads to improvement in yield because we can now translate it in control loop. We're able to gain about 50% gain in this case, defects, as we have reported last year or early this year on SPIE. Finally, our EUV high NA extension. If you extend the roadmap beyond five nanometer, beyond the D1Z, you see that even at some point, you have to be forced to use EUV in double patterning mode.
That's technically possible and more than happy to do so, but the cost of this double patterning one eye to three is one, but doing it with EUV is second. We believe we should aim ourselves and try to stay out in EUV double patterning, and provide customers with solutions when they could do so. For that, we have ideas on improving the resolution of the tool, which is again, able to reduce for the sub 5-nanometer node, the cost by 40% and a simplification in terms of an amount of passes by 30%, which allows you to stay on more slower track on the right-hand side. In order to do so, we are scaling up our optics, and one of the dramas of scaling up our optics is that the machine gets bigger and we require another major platform.
This is suggesting a different platform of optics. You see that here it's been animated, where we need to have major innovations in the optics. Therefore, we intensify our cooperation with our partner, Carl Zeiss, where we are making innovations by adding mirrors and even still go up to 2 times more transmission. Why is that important? People thought by increasing NA, reducing transmission. We like to increase transmission because the cost of photons is relatively high, and we have to make sure we stay on track with our cost roadmap. We have had some scaling issues, and this shows you the challenge we have. We have the mask and the wafer. This is just a pictorial of our current 0.33 NA system. If we just go to a higher NA system, we are blowing up the angular spread on the mask, which could be a showstopper.
We may not be able to scale to high NA if we don't do things differently. We could increase the magnification to reduce the angular spread, but then we have to be incompatible with the current mask infrastructure. We do like to introduce the high NA without making a major disruption in our mask infrastructure and our customer infrastructure as well as source need. The invention we have, we make what we call a kind of an asymmetrical mask, where we only reduce the angles in the direction we need it, and we use the angular spread in the other direction, allowing us to stay compatible with the current mask infrastructure, but cutting the field size in a factor of 2, which has some additional productivity challenges, as I will show.
This looks very similar than the cinema, where new screen sizes have been introduced by 16 to 9. We have to be compatible with the film camera, so the film aspect ratio stays the same, but your screen changes to 16 to 9, and you're using their anamorphic, I cannot spell this whole thing, lenses. If you go to the cinema, you have an idea that this technology already applied, except a different resolution. The semifinal slide is this, that we are all doing that. We're going to high NA, we're going to cut the field size, but by major innovations of stage technology and transmission gain in the lens, we plan to at least gain 25% in productivity. We like to go up in productivity substantially, and we like to get substantial simplification of the process.
That even allows us to introduce those High-NA with the current sourcing architecture. I'm not saying we're staying at 250 W target of a source. We may increase this to 500 as we go, but it's not critical of us introducing the High-NA system. That leads us to the overall roadmap. This is the 33/3400 product offering, as we see. Also here, productivity to right overlay vertically. Also here, we are upgrading our customer base going from NXE:3300 to NXE:3400. However, with the new High-NA system, we will be able, needed to make a complete new platform, which will be the next challenge for the next 5 years in ASML, going to our next contribution, what I say on Moore's Law.
With that being said, I'd like to conclude that I think Moore's Law to continue, I always may say likely to continue, but the investor relations change will continue. I cannot promise a continuation of Moore's Law forever, but I try to make it a bit plausible that if things are doubling for 100 years, it's very unlikely the thing will stop in the next 5 years. It will go differently, but it will continue. Also, I suggested that the application industry can use it. That drives us then with four major priorities, because in order to stay on the roadmap, we have to industrialize EUV. We have shown EUV works, but now we have to see we can support EUV in the field. We keep on running EUV machines every day, every minute.
We continue to see substantial need for our DUV products, the DUV products need to be mix and match with EUV, needs to be becoming the perfect machine. Nobody likes to talk about DUV, it just has to work. We have holistic lithography, which are answering, connecting the complex little with the process integration and try to go to the heart of our customer, say, try to control the critical dimensions and the critical overlay in a way we look into the real application of the customers. For that, we probably have to enhance unique metrology system, both optical and E-beam. It's not only about E-beams, both optical and E-beam. Finally, we are on the world, a extension of our current technology, which we call High-NA. With that, I'd like to thank you very much.
Thank you. In the next 25 minutes, I would like to give you an update on our EUV program, the role of EUV and its business opportunities. I kept the agenda very simple. It's only three words. Why are customers so interested in this technology, why do they want to get it into their manufacturing environment? The second part, it's about a third, a third, a third of the slides. The second part is about how are we supporting EUV introduction and what is, for instance, the data set that we today have, where our customers are happy with and also where some room for improvement is still there. Thirdly, when. When do we believe that our customers will start using EUV in volume production? That's the third part of the presentation. Let me go into the why.
Some of you might have seen some of these slides before, but I think it's important to keep reiterating why our customers are so interested in the technology. What you see here on the left-hand side is the amount of process steps it takes with the complexity that Martin already showed earlier, the amount of process steps it takes, for instance, in an immersion flow for logic application, if you go from multi-patterning, you can do litho etch three times, or you do it even four times. There's a tremendous increase in the amount of process steps that a customer needs to apply. When you move them back to a single exposed technology, like Martin said, for EUV, you see a strong reduction in the complexity. The amount of layers is less, and that typically translates to less complexity in the process flow.
For logic and memory, it's fairly similar, although in memory, the complexity is maybe slightly less than in logic. Overall, reduction of complexity is a very key improvement step if you go to EUV. How does that translate into some of the litho requirements? What you see in the next couple of animations is the amount of litho steps, which you see in the table below, and the amount of metrology steps that are needed to make sure that what cracks it at the beginning, you put the second layer on top of the first, the overlay accuracy. You have to measure that. You have to measure that in order to make sure you're at the right position. The lines that you see, the arrows that you see, reflect the measurement steps, and the blocks basically are the amount of litho steps needed to create the layers.
Basically, you go from bottom to top, that's the amount of layers in what you see more and more multi-patterning steps if you step through the technology nodes of our customers. It's becoming extremely complex. What this is reflecting is basically the amount of exposures, the amount of mask steps a customer needs to use, and the arrows, as I said, the amount of metrology steps becoming extremely complex, therefore also prone to maybe more errors than with a single exposed technology. If you go, for instance, in the seven nanometer logic process flow, if you would switch a number of layers to EUV, again, it becomes a lot simpler. Reduction of complexity, reduction of measurement steps, probably increasing the accuracy with each positional edge. How does this translate to cost benefit?
What we did here is compare a design flow using immersion multi-patterning, you see that on the top row, compared it with the replacement of a number, in this case, nine layers by single exposed EUV. Of course, you still will have a number of multi-patterning, also single patterning immersion layers left. Obviously, these technologies will be applied in parallel for many years to come. What you see here, especially in the mid and the back end of line, you see essentially less process steps, which translates to a cost reduction. In this case, we calculate it to be about 12% lower cost if you would replace a number of the, again complex multi-patterning, layers into a single EUV layers. That's not the only benefit. It's a cost benefit, always driving our customers, but there's more to it.
The fact that the processes are more simple also essentially increases the yield, the overall yield. Obviously, customers like that, estimated about 9%. Last but not least, what is very important, if you look at the cadence, you heard a cadence of two years, two and a half years, even three years, our customers see a significant reduction of the expected time to market. Again, it's simplicity. It's less complex processing for them, and it basically means the learning curve is steeper, and that brings their time to market, in this case, again, maybe about six months faster than if you would not do it. Again, a lot of customer benefit in replacing a number of multi-patterning layers by single patterning EUV. How are we doing? How are we doing against the requirements that our customers set us out for in volume manufacturing?
What I'd like to do is take, after I sketch an overview of what happened in the last couple of years in terms of wafer output, in terms of even availability, but also source power at ASML versus in the field. It's all nice that we share data with you, what we generate in our factory, but what it's really about is what do the customers have data in their factory. This shows everything in the next couple of slides. I will also share some of the customer data that we have recently seen come out. How does the landscape develop in terms of performance? We took basically the kind of the investor meeting two years ago as an anchor point to visualize this.
What you see here is the amount of wafers per day that customers have reported, starting with IBM a couple of years ago, and actually Martin just showed you some data from TSMC, where they showed 1,500 wafers a day for a number of days in a row. We typically are a little advanced in our factory with the amount of wafers per day or the powers associated with supporting that, simply because we need to demonstrate it first in-house before we roll it out to customers. We qualify it in-house, and then we make it available to our customers. That's why you see some of the blue numbers, which is the power at ASML, be higher than at our customer sites. Makes sense. Our customers, typically, what Martin showed is some productivity numbers.
We are now in the range where we are well above 100 watts in the customer's hands. Customers have different types of machines in their factories, so not all systems are in that configuration. We've rolled out to our customers a source power well above 100 watts to 125 watts, and that gives you about 85 wafers per hour. Combining this with availability, and this is where the area of improvement still is. What you see in the green bubbles reflected is what we typically measure and our customers measure, is a four-week average of the availability. What we plotted here is the progress in the best four-week average over time, gone from 55%-ish to what we're seeing today at one customer site, above 90%. That is not the average. The average is more between 70% and 80%. I will show you that in a second.
Last but not least, this has led to progress in the amount of system orders, which obviously is also what things are about, especially also in this environment, but also in our own business environment. In all the sketches kind of the landscape of improvements over the last few years, what I'd like to do in the next couple of slides is share with you some of our customer data. Maybe some of you were actually in EUV Symposium last week in Japan, where a number of our customers presented their latest results. I think an important one is, for instance, this one, particularly from Intel, where they have actually applied EUV in a 14-nanometer pilot line. What you see in this chart is basically a year's worth of CD data, so the imaging part of the 3-step process that Craig described.
You see the stability of their critical dimension for, in this case, a via layer. We're very satisfied with it. It's stable. It doesn't change. Even if you bring in, for instance, a 2nd tool of a different type of generation, is what they did. You see the red and the blue symbols in this chart. Customers, in general, are very happy about the imaging capability. I did not pull up an overlay slide, but that's actually very similar. It's very stable performance over time, and that is ultimately what our customers are looking for. This is where our customers are driving us the hardest right now, is on availability. It's not just the average of the availability, but it's also the fluctuation of the availability, as Martin mentioned. When we talk in terms of improving consistency, it is basically about this.
It's about wafer output. It's about availability of the system in their hands. Although the average, as you can see here, has gone up quite nicely, what customers want us to improve on is especially the day-to-day fluctuations. Again, it's not about the quality of the images or the quality of the overlay, but it's the wafer output and the availability of the system itself. The trend is good. The variability needs to improve. We have a number of innovations that we are rolling out. We have a number already applied into our new systems, but one of them is a critical one. It's called the droplet generator. Maybe you're familiar with it. It's a module.
It's a functionality in a machine that basically spits out 50,000 times per second, a small, thin droplet, which is basically the source, the fuel of the EUV radiation that we use for litho. What we see here on the left-hand side, you see some TSMC data where they actually confirmed indeed a more than 4X improvement in the runtime. That means this droplet generator basically runs out of tin. You can refill it. You can reuse it again, do that a number of times. Obviously, if you don't have to replace it, but you can refill it, what you see is that the uptime or the availability of the system goes up. It's recognized by multiple customers that this was a good thing to do. This is a good innovation to increase the availability of the system at our customer sites.
We have a roadmap in place for improvements. We shared a similar format actually two years ago. Today it's, let's say, the end of 2016. What we typically see in the field is this 70% to 80-ish percent of four-week average availability. It's a good increase, but it's not sufficient. In volume, our customers require more than 90%, but also the variation on the numbers need to be very small. There are a number of innovations that we are developing to support those improvements, which you see on the right-hand side, where it's labeled 2017 and 2018 targets. They're mainly focused on three items. We have more innovations coming out for the droplet generator. We want to go into an automated tin refill mode, where it's basically a continuous flow of tin going into the droplet generator, so you don't even have to refill it anymore.
Improvements in the seed table, where actually the laser light is generated. Last but not least, on the drive laser itself. The drive laser, which is an issue for our customers, the improvements in reliability. That combined with a number of reliability improvements in the scanner will bring us to the 2018 target of 90%. Again, the variability is substantially smaller then. Wafer output is essentially driven by two components, it's the throughput, the amount of wafers per hour, and its availability. The next two or three slides are about the productivity, the wafers per hour. As I said, today, we are rolling out systems with a source power in about 120, 125-watt region. That gives us about 85 wafers per hour. At our own facility, but also here, as you see at our customer facilities.
This enables customers to use these 1,500 wafers per day. Three days is fantastic, but there's a lot more days in a year. What we need to do is make sure that this is available for our customers all the time. Again, this comes back to the availability improvements that were already mentioned. Also there, we have a roadmap in place. We know what to do. If you want to summarize it in a few points that need improvement, it's the source power, that's an obvious one. But what you might not know is that we've also improved the transmission of the optics. Martin alluded to the next generation for High-NA, but also in the current 0.3 NA systems, we continue to improve the transmission, and we do that, for instance, by changing the coatings or maybe some other parameters. Improving the transmission is one.
Last but not least, also on stage performance, which you can see in the 2017 bucket, we reduced what we call the swap time between wafers, and also that helps us to increase throughput without having to increase source power. What you see then for next year, the range is actually between, let's say, 85-ish and 125 wafers per hour. That's partly driven by the various configurations that will now be in the field at our customer site. This is not all, let's say, our top-of-the-line product. This is a mix of the various things that are already there. That's why you will see a spread in throughputs that are there, hopefully next year or planned to be there next year. We also will not stop at the power levels and the throughputs that you see in the 2017 timeframe.
There's always a drive for more wafers per hour, with faster processing, because as Martin said, this basically drives the cost down for a customer. We will continue to drive improvements in the throughput, be it in the source, be it in the system itself, be it in optics from ZEISS. On the scanner side, in summary, I think, we're good on the litho part. The overlay and imaging, as we said, we first have to create the image, then you have to put the images on top of each other. That's all well under control and meeting the customer requirements. The repeatability of the process, so getting many wafers out, that is where our focus will stay for the foreseeable future. Around that, it's not sufficient.
Around that, you also have the infrastructure that needs to mature to get ready for volume introduction, it's been separated out into a number of attention points. Whereas the mask blank, you have the processing on the resist side, which we added on the bottom. You have the inspection of the masks, and you have the inspection of the blanks, but also you have the mask handling. There's a number of components that need to mature together with the scanner side of the technology. We kind of color-coded it where we believe things are essentially ready for 7 nanometers or ready for 5 nanometers or even beyond that, and show where we believe the key improvements are still required. I'm not going to discuss nomenclature about node names. I think it's probably handier to talk about introduction timings, the 2018-2019 timeframe, and next generations beyond that.
We believe for 7 nanometer, many things are in the green. There's room for improvement on various areas outside the scanner for 5. Also, this was shown last week at the EUV Symposium, and this is a compilation of a few slides that one of our customers showed at the conference. They basically show 8 key components in the infrastructure, also show a little bit of the progress. If you just look at the color coding of the various components throughout the years, it is about EUV mask inspection, it's about actinic blank inspection, it's about pellicles, it's about EUV blank quality, and last but not least, also actinic pattern mask inspection. There's been concerns about that. Let's not forget, pattern wafer inspection is available, there are also alternatives already for actinic pattern mask inspection today.
That depends a little bit on the customer, which types of technology they prefer, which they believe is needed to go into volume. Next couple of slides, I'd like to show a few of the data slides supporting some of the yellow boxes. The color coding in this case was green, is basically ready today. The yellow ones are the ones that need development before it goes into volume. Obviously, red speaks for itself. There is a significant amount of progress still required for that. I'd like to share a few slides on mask blanks, on pellicle, and on the resist. First, on the mask blanks, remember the pattern is on the mask. Defects in the fabrication process of the mask could result in defects printed on the wafer.
Our customers are driving the blank vendors to essentially zero particles, but it's more zero particles of a certain size. Here again, you see progress of the customers where they trend out the progress over the next couple of years, one with and one without describing the axes. There is a clear progress in defect reduction in the manufacturing process of the blanks, and this directly also translates into yield improvements, when you use these blanks for printing. There is a good progress chart over the years. As Martin said, with other trends, there is no reason to believe why this would not continue in the next year or two. A key enabler for some of our customers for EUV introduction is the use of pellicles, EUV pellicles. Here you see one, actually developed by ourselves.
We have taken up the challenge to make pellicles available for our customers. Pellicles, like in DUV systems, prevent particles from reaching the mask surface itself, so particles stay out of focus, and they will not image on the wafer. Here you see a full-size picture, full-size pellicle. One of the many metrics that we investigate and qualify is its durability, its lifetime, its thermal load capability, and obviously also imaging uniformity. Last but not least, its prime function is to keep defects away from the surface of the mask. We are basically in the process of qualifying them. Customers are helping us there. They are also using pellicles in their systems, basically to progress this further and get ready for volume introduction.
On the resist side, I think an important parameter in the whole productivity chain, obviously resist primarily is there to transfer the image from the mask onto the wafer. If the dose is high, for instance, as being used, it basically costs you wafer throughput. The whole industry is driving not only the imaging capability, as you see in the SEM images for, in this case, 16 and 13 nanometer half pitch lines and spaces, but they are driving the dose, because that drives productivity. They are also driving the imaging capability itself, the imaging quality itself, which is reflected in the line width roughness numbers you see on the bottom row. There is, of course, a number of other parameters also important, but these are two of the key drivers. The image has to be right, and it has to be done fast and many times per hour.
A factor of two improvement in the dose, that translates to roughly a 50% increase in productivity. Good progress. When? The third part of the trilogy, when are our customers planning to start using EUV involved in production? You saw this slide from Martin. What I added basically is combining some of the public statements that some end users have made, and those are reflected in the stars that you see on when they believe they are going to introduce EUV. You see a lot is focused in the logic arena. It is focused in the 2018, early 2019 timeframe. You see memory slightly behind that, although there is also now a significant increase in the activity there and also the interest. It is in the performance memory in the DRAM side, where also EUV for specific layers can become extremely attractive.
This is roughly the timeline where our customers are currently looking at introducing EUV technology. Again, one of the closing remarks of one of our end users last week was this, where TSMC quoted that they will use EUV extensively in their 5 nanometer technology node. They also acknowledged the solid progress, and at the same time, they also bring up things like, okay, but availability still needs to further stabilize and reduce in fluctuations. Especially on the mask side, they want us and the rest of the industry to further improve on reducing defects in the mask blank, and the use of the pellicles. Making pellicles available in the right quantities with the right quality. What we put together is a compilation of a number of public statements of some senior executives of our key customers.
This is what some of the logic customers are currently quoting. I am not going to read through all the statements they make, but they all state roughly the same as the 2018-2019 timeframe. Depending on the customer, they talk about a certain node name, or a certain, let's say, indication of resolution. You see here some of the leading NPU and logic customers quoting similar timeframes. If you look in the memory segment, especially in the DRAM segment, also here you see statements about, in this case, Hynix and Samsung, where there is opportunity in 2018, 2019 for D1Y, which is like the mid-range of the one let's say the 15 to 16, 17 nanometer range of resolution, both Hynix and Samsung making statements like that.
The roadmap to support these customer introductions, as Martin showed it, we have currently in the field 3300 and 3350s. We are starting to finalize the qualification of 3400Bs. On the right-hand side, as Martin indicated, you see the key metric that our customers are looking for. Besides the productivity part, the cost reduction part, you see the overlay requirements. Again, this will be followed by our High-NA change of platform. Towards the end of the decade, early next decade is when that is going to be ready to roll out. In between, we will probably also continue to extend and improve the current NA, the current 0.33 NA systems, be it in overlay improvements or also in productivity improvements. Our design DNA is similar as it is in DUV.
The install base of our customers have to be able to be upgraded to the next generation tools. Again, that is reuse of the capital. It is of prime importance. What does this translate to? If you look at some of the capacity that, for instance, typically logic or in this case, DRAM performance memory companies are looking at. How does it translate from wafer starts per month to EUV layers, to amount of tools that they require? Here you see just a fairly simple example and calculation of what it can mean, and this is, let's say, for individual customers. If you look at logic, customers are typically looking at, for instance, 45,000 wafer starts per month. That is about 1,500 wafers per day.
If you can go anywhere between 6 or 10 layers of EUV, this also translates to about 7 to 12, in this case, EUV systems in a fab. You can do the same math for performance memory or even storage class memory, although that is somewhat later in time. You get a first indication here of an amount of systems in a fab, again, per customer. Wolfgang will come back to this a little bit more in his presentation a little later on this morning. Where are we today with our supply chain? ASML first on the upper left, you see expansion of our clean rooms, started in 2014. The pictures today look very different. The shell essentially is finished. We are filling cabins with new EUV space.
We also have more space available in the new clean room, which is on the bottom left of the middle top picture. It is kind of hard to say if you do not have a pointer. That is where the expansion is for the EUV clean room. The shell is there, and we can expand the amount of cabins, make more cabins available upon the market need. Two of our key suppliers you see on the bottom. Bottom left, obviously, Carl Zeiss in Oberkochen, Germany. They have expanded their facilities significantly to enable production of EUV. Also, last but not least, TRUMPF, our key drive laser supplier, in the source area. Also, they have announced their clean room. It was actually already a while ago, they have announced building and expanding their facilities also to enable the growth of EUV.
With that, I come to the conclusion slide, similar to also some of the statements we made in our quarterly results. If you look at availability, again, that is one of the key driver, for improvement from our customers to us. Availability itself is okay, the variability of it still needs to be significantly improved. We have our means in place to do so, now we have to show it. We have to make sure it gets into our customers' hands. Secondly, on productivity, 1,500 wafers per day. We have shown the capability. We need to repeat it on a daily basis. That is again, what our customers are asking for. The numbers are right, it has to be repeated all the time. On infrastructure, you can summarize it in various ways.
I think most of the components are either already there or are on track to be ready on time for HVM introduction. Last but not least, it does look like our customers are looking at a 2018, 2019 timeframe. Again, I am going to park discussions on nomenclature of nodes, the timing of it is very similar. With that, I conclude, and I would like to give the floor to Christophe. Thank you.
Thank you, Hans. Good morning, everyone. I'm going to talk about holistic lithography. I think you already heard this morning several times, Peter, Martin, using terms such as patterning, pattern fidelity control, holistic lithography. All those terms means basically that for our business, it's becoming important to not provide any more point-to-point product. It's not enough to give a scanner, it's not enough to give a metrology tool. What's becoming very important to continue to drive Moore's Law is to bring those product together and help the customer basically to use them to improve on product performance. We have been working on holistic lithography for many years. In the last few years, in fact, we have seen customers starting to strongly adopt our product.
We have, at this point of time, proven solutions, and this has allowed us to basically create a nice business opportunity with a year-on-year growth of about 20%. The good news is that this is not stopping. In fact, the appetite for holistic lithography is increasing. We are very closely working with our customer, and this allows us basically to fuel our roadmap also with new product. We'll continue to basically bring those product. This will help us. It's already helping us, in fact, to support the EUV transition. Moving forward, we expect basically to continue to grow on this business. One of the big things we have to address is what we called the image quality. We talked a lot in the past about image placement, which ASML call overlay. This was consisting basically in just aligning two different mask together.
We did that in the past because lithography was about single exposure. I think Martin explained very well this morning that this is a bit the past. Today, in order to print a pattern, customers are going to use not only a lot of different mask, but they're also going to use different etch steps. We have to make sure that our solution moving forward are going to support that. This was one of the motivation for the HMI acquisition, and I will spend quite some time on this this morning. We believe basically that if we continue to address those opportunities, if we bring basically the HMI product portfolio to help us to do that, we are going to continue to create at least a 20% year-on-year growth moving forward.
We do not see basically this business slowing down, I would say, all the opposite. The next slide you have seen already today, you have seen many times in the past. It's still, I will say, the foundation of holistic lithography. This is a holistic triangle with three different components. The first one is, of course, the scanner. I think that Hans and Martin have explained already very strongly that this is still, of course, the foundation of holistic lithography, a lot of our energy basically is to improve those products. On top of that, there is two additional technologies we are developing very actively. The first one is metrology. Why metrology? Metrology, because you need to be able to see what is happening on our customer wafer.
We want not only to provide tools, but we want to know the effect of those tools on the customer wafer. This is why, moving forward, we in fact see the use of more and more metrology, because those metrology tools will provide us data that we can use basically to understand and control the process. This brings us to the third part, which is the computational lithography, and what we do there, the idea is basically is that we can use design model, we can use process model in order to use the metrology information we collect and describe basically what's happening with the process and what is the effect of this process on the customer device.
With a limited amount of data, we are capable basically not only to describe exactly what's happening on the wafer, but we're also going to be able to use this information in order to control back the process and therefore improve the yield of our customer. I'm going to go a little bit into the detail of all of this. I want to start basically with an animation. I went back in our old library and I took an animation we created basically when we launched the TWINSCAN platform. What you see on this animation is two things. If you look at the left part, you're going to see what we call our metrology stage. We have 2 stages on the scanner. I think all of you are aware of that.
One of the stages, of course, is exposing the wafer, processing the wafer, the other stage is going to measure the wafer. We spend already on the scanner as much time measuring than we spend processing. A lot of people believe that ASML started with metrology when we introduced Yield star to the market. The truth is we have always done metrology. From the beginning, we knew that metrology would be important to support our litho process, and this is the reason why we had this stage basically on the platform. Not only we always did metrology with the scanner, but in fact, the scanner is the only tool in the whole fab to measure 100% of the wafer. Every single wafer is going to go through a metrology step on the scanner.
I will talk a lot about sampling, I will talk a lot about those things moving forward. When it comes to the scanner, we measure all the wafer. That's the first thing. The second thing, if you look at the other stage, the processing stage, you can see that, you see this laser spot, basically, this means that we are exposing the wafer field by field. This is again, the only tool that does that. Etch tool, deposition tool are going to process the wafer all together at a wafer level. In our case, we are going to basically expose the wafer one field at a time. This is important because for every field we are going to expose, we are capable to modify, if you want, the setup of the scanner in order to control the process.
Every scanner, Deep UV or EUV, is being built with a lot of different knobs that are used to improve, when necessary, the overlay or the imaging. This is what you see here on the right. This is still very important, and I would say this is still at the core of everything we do in holistic lithography. The ability to have not only a tool that is going to process the wafer, but a tool that can become, by default, a place also to improve the process and therefore the yield. On the next slide, I'm going to try to explain to you a little bit why metrology and why model are important. If you look at the left, you see an EUV scanner with a EUV overlay map. The overlay map is our champion data.
We see less than a nanometer overlay, which is of course a very good number. The question is, of course, what is this overlay going to become on the customer wafer? That's not going to be a nanometer. This is what you're going to see on the two other maps in the middle. On the right, I put a painting to help you a little bit to see how this works. What I'm going to show you is how we use metrology in order to basically understand the process on the wafer. We start with 100 points. You see that with 100 points, you can't really see what's happening on the wafer. The wafer 1 and the wafer 2 look very similar. You also can't really understand what is the picture on the right.
If I go to 200 points, it's still very difficult to see what is the difference between the maps. You start to see that some of the vectors are looking different. Some of you may already be able to recognize the painting on the right. Going to 300 points, most of you have recognized the painting on the right. Still, if you look at the wafer, you start to see more differences, but you don't have yet a full description of what's happened. This being said, you cannot measure as much as you want, because every time you're going to add more points, it's going to cost you more money. Customers are going to limit, by default, the amount of metrology.
The good thing is, if we use this metrology as an input to our model, our model are going to be able to tell us, without a limited amount of points, what is the real fingerprint. What you see here, basically, is now the total description of the wafer fingerprint. You see that they are very different. You see that we can basically, from this information, control the wafer accordingly. How does it work? It works exactly in the same way it worked for you with the picture. Why did you recognize the picture after 20% sampling? You did because, in your memory, you had a certain image of this picture. You had seen it before. That's a bit true with what's happening with process.
We can describe basically with a limited amount of metrology what is happening, because we have seen this information before, because we know how the scanner works, because we know how the design works, therefore we can predict, with a limited amount of sampling, what is going to happen on the wafer. This is why every time we are going to talk about metrology, we are also going to talk about model. If you translate this now into the business model, back to the triangle. As I said, we're going to use metrology in order to get data, the model, and then basically the control on the scanner. If we look at the overall holistic lithography business, you see that about 70% of this is going to be software.
This has to do mostly with model and control, and about 30% will come from the metrology hardware. From the 70% of the software, about 45% is directly related basically to the scanner itself, because these are the software we are going to use to control it. This is why, of course, I think Peter mentioned that already, and Wolfgang will stress it again, the gross margin of this whole business is, of course, a very good one. Martin has been showing this slide already, and this is basically what we have done so far with holistic lithography. The idea is that we use metrology, we input the data to our scanner, and basically we use that to improve the yield.
If you understand that, if you understand basically the last few slides I showed you understand basically what we have done so far with holistic lithography. But of course, this is the past, and I guess you didn't come here to understand the past, but to get a glimpse of the future. This is what I'm going to try to explain you now, moving a little bit to what is coming next. What is coming next? Martin has shown this slide already. I will spend a bit of time on it. I think what we explained you already is that in order today to create this final pattern, customers have to use more than just one mask, as we used to do in the past.
This is going to be created by first creating a very dense 1D dimension structure, and by adding a few cut masks in order to get basically to the final pattern. Now, if you look at the whole thing, you can count, it's about four different etch steps, and this is three different lithos steps. You have seven different process steps, basically, in order to get to this picture. What is becoming important now is not to make sure that only this picture is aligned with the previous layer, but to make sure basically that what you see on your wafer is going to match exactly your design intent. You're going to want to compare basically this picture on the right with the picture of the designer, the device people wanted to have in the first place.
This is what we are going to call pattern fidelity control. Pattern fidelity means basically that we want the image to match exactly the intention. Control means basically that we are going to correct, if necessary, the litho step, but potentially also the etch step in order to make sure that we get there. This bring me to this more sophisticated or comprehensive approach to control. You see, as you saw before, the overlay loop. We are still, of course, going to control overlay using metrology and the models. On top of that, what is better to check the fidelity of your patterning than to look at it with a very high-resolution tool? This very high-resolution tool is going to be E-beam. E-beam is basically entering this control loop. Can you just grab the issue with your microphone? Is it better? Yeah. Okay.
The E-beam tool is going to enter basically this more comprehensive control loop. I think you all know that for many years, one of the major challenge with E-beam has been the speed, right? It's been a long way to get E-beam to high volume manufacturing because the tool is, of course, not fast enough. How we are going to address this? What we are going to do basically is use our scanner metrology. I told you before, we measure all our wafer, use our YieldStar metrology, and use our model to tell the E-beam tool what to look for. Instead of going blindly basically across the whole wafer, which could take a lot of time, we are going to guide the E-beam tool to the location of interest, which we can calculate.
The E-beam tool will validate basically on this location if there is or not a problem, send back this information to the model, which in the first place was used to find it, improve this model, and also send back the information to the scanner in order to, again, control and improve the process. This is the story. To go a little bit more into detail and to explain basically this connection between model metrology and scanner, I'm going to show you a few example. What you see on the left here is a model of a pattern. This is the way, if you want to initially start to try to describe your patterning. You do that by simulation. What you see is basically that the left part is quite different from the measure piece, which is an E-beam picture of the same pattern.
The metrology, the E-beam image, is going to be used to improve the correlation between those two images. This is what you're going to end up with. Now if you want to do that, and it's happening today already at customer, you need to measure 1 million points. You need to measure 1 million points in order to make sure that your model is good enough to be used to predict anything. I don't know if you know how long it takes today to measure 1 million points with a SEM. It's about 20 days. 20 days of work basically by a customer in order to be able to come to a point where the model is helpful enough. Once you have this model, the next things you are going to do is use it to guide your metrology tool.
Because if you can model your process, if you can model your design, you know pretty much where problem may happen. If you do that, you're going to be able to look only for the area of interest. Why is it important? A lot of people talk about wafer inspection. Today, if you look at the speed of our scanner, I think Hans was mentioning that EUV is going to aim for 1,500 wafer per day. Deep UV today is at 4,000, 5,000 wafer per day. An inspection tool allow you to measure about 10 wafer per day. 10 to compare to 1,500 or to 4,000. Less than 0.1% of the wafer we expose on the scanner are going to go through optical metrology.
This means that if you go for this path of just trying to inspect the whole thing, you are not going to be able basically to control the scanner. You're going to be able to monitor and find big problem, but you are not going to be able to control. If you want to control, you have to go to much higher sampling. This is very important. If you do that, what I'm going to show you now, we aim to provide for every single wafer map that goes through the scanner, every single wafer that goes through the scanner. We're going to combine the metrology information, we're going to combine the model. What you see basically in the middle is the wafer map showing, as a result of the metrology and the modeling, what are the dies on the wafer that have a problem.
This is done within a few seconds. This is done basically as we can process the wafer. You have a full information, full wafer, every wafer. This information is going to be again given to the scanner, because the other things we have been going after for many years is the ability to not only find problem but also correct it. This is what you're going to see on this slide. You have again the same wafer map showing the problematic die. This wafer map is being injected into our scanner control software. We use the scanner knob, we are capable to remove some of the problem. You see in this case that more than 50% of the die are being fixed just using the scanner knobs.
We go from a situation today where you monitor basically problem on the wafer, using only a few percentage of the wafer, to a situation where we are going to get information for 100% of the wafer processed in the scanner. We're going to be able to control those wafer, and as a result, improve, I would say, the yield on that. This is quite a big change, of course, compared to the technology used today by customer. The next things when it comes to E-beam, that's also very important. Martin was talking about what's happening with our memory customer. I think he was mentioning the trend, going towards 3D integration as a way basically to extend the road map.
The problem when you look at 3D structure from a metrology point of view is that you don't have many tool who can tell you there is a problem. The reason for that is that as you integrate, you increase the complexity, and it become very hard, for example, to reach out to the bottom of a contact to find out if there is a problem or not. How this is done, E-beam tool has been used already for several years to perform what is called voltage contrast inspection. What voltage contrast inspection is doing is very simple. The E-beam tool is going to bombard the wafer with electrons, and depending if a contact is open or closed, the electron will be evacuated or not through the contact.
If they are, you have a certain number of electrons that are recollected if they are not a different one. This is why, if you look at this picture at the center, you see three contacts that are black, and this is an indication, basically, that something went wrong in the stack. This method today is the only metrology method to find out, in fact, if there is a good yield or not on very high aspect ratio structure. Once you have this information, as always, it's going to be used basically to describe what's happening on the wafer. Again, give a different type of fingerprint. Fingerprint that can, again, in return, be used to potentially, in this case, improve your etch process.
Same type of idea, and you see here that, for example, with the addition of voltage contrast metrology, ASML has the ability also to start to work a little bit more effectively on the very high aspect ratio 3D structure. The approach we'll take there is similar to what we have done with overlay. We are going to try to create a control loop for our customer. This is voltage contrast. The other application, which of course, you understand that from Hans' presentation, is becoming very critical for ASML, is the EUV mask inspection. HMI technology allow us to look at defect both on the reticle and on the wafer. This is one thing.
What's also important is. We've not talked about this in Hans' presentation, but if you look at this whole market of mask inspection, typically, customer are going to buy only a few tools. As a result, the supplier will have to charge a very large amount of money in order to get basically the investment back. The advantage of using E-beam for mask inspection is that you can use a technology which is already used for wafer inspection, which basically give us a major cost opportunity. We don't have to go and develop a very specific tool to do the mask inspection. The technology on wafer, the technology on the reticle is going to be the same one.
This become very important for us because we do need to look at reticle defect, customer are very clear that this is one of the key factor for EUV insertion. With, again, this technology, we expect to be able to do that and to support, I would say, very aggressively the EUV insertion, as well. This is a little bit more conceptual table. What I'm going to explain you here is a little bit how we see the market. What's going to happen moving forward. This is a graph with two axes, of course. The bottom one is showing basically the percentage of wafer we are sampling. Remember, the more wafer you're going to sample, the more wafer you're going to measure, the better you're going to be able to control your process. The Y-axis is showing the measurement resolution or accuracy.
There, typically, the smaller the number, the better it is to find small defect or to drive an accurate, for example, overlay control. Then we have three different category: R&D qualification, high volume monitoring, and high volume control. We make the difference between monitoring and control. How do we make this difference? It's all based on sampling. If you look at R&D folks, they're going to measure only a few wafers. That's good enough for them. If you look at monitoring, you need to measure again maybe less than 1% of the wafer. What you do, you make sure that you don't have a big catastrophe on your process. When it comes to control, as I said before, ideally, you will measure 100% of the wafer because you want to know basically, all the information you need.
Practically, with the use of model, this can be a little bit lower. If I start with the blue box. The blue box is what we have done with overlay. For overlay, we have a tool, metrology tool, which is very accurate. We measure every lot. Thanks to the integrated metrology, every lot is being measured, and this allow us now for a few years to help customer to control overlay in their fab. If we look at the orange box, this is what HMI is doing today. The speed is not very high. They support R&D customer mostly, right? They are going to use basically their tool to debug, I would say, the process. In the middle, you have basically the application supported by high-resolution optical metrology. This is fast enough to monitor.
It backs to the 10, 20 wafer per day I was talking about, not fast enough to control. As you know, it's been a discussion between e-beam and optical for many years. There is a difference of resolution, of course. The optical tool will be limited to about 10 to 20 nanometer type of defect. This is pretty much today. If we look at our opportunity in this configuration together with HMI, that's about EUR 700 million a year. Of course, we didn't go and acquire HMI to do that. The reason we went and acquired HMI is to do what we did already with overlay, and to take basically those orange box all the way to the right for control. What we want to do, again, is combining the e-beam metrology by accelerating it with multibeam.
This is something we're going to work very intensively with HMI as well. By adding our model, we want to use this metrology tool for control. If you look at the middle column, monitoring, the two new green boxes, what used to be HMI dream. HMI for many years have been trying to catch up basically on optical inspection speed, and the dream was to be as fast as they are. This is good for monitoring. That's still not good enough for control. That's the reason, again, why we're going to have basically the type of technology we have for overlay and supplement the e-beam speed with model in order to be able to use it in control. If we do all of that, we could still argue, I believe, quite a bit on the number, but we believe that the opportunity for ASML is EUR 2.3 billion.
I think Wolfgang will explain later on that this is a total opportunity. That's not, of course, what we plan to address, or to capture by 2020. I think this is important to understand that. We take basically the whole product from R&D all the way to control. The only way to do that is really to combine HMI and ASML. To conclude, I want to go back to our holistic triangle. I think Martin also has shown that we are going to add HMI, which basically allow us to create metrology for pattern fidelity. We move from overlay to something far more comprehensive for our customer.
This also give us the ability to go a little bit beyond lithography when it comes to control, and potentially also help some of our edge colleagues in the market to co-optimize their tool with our own system. We also have quite some work ongoing with a different player in order to, I would say, go beyond just litho. This is my last slide. Thank you very much. I'd like to give the stage to Wolfgang, who is going to present our financial model. Thank you very much.
Thanks, Christophe. I don't think I need this. See whether my microphone works. Good morning, everybody. Green. Okay, I got it. I want to cover four areas with you today. I want to spend just a little bit of time looking back, how we have invested and how we have created shareholder value over the last couple of years. It also tells you a little bit about what we are. I want to dig into continuing growth. I want to pick it up where Peter left it. Look quickly at the growing industry and how we will add value, and how that value addition to the customer translates into revenue for us, while making sense for the customer.
We're basically looking at the number of wafers needed, of course, it's not just wafer growth that drives our revenue, but also increasing litho intensity through node transitions, then you add service on top of that, you're getting to our total revenue picture. We're going to address that, then transition once we have established what we can do from a revenue perspective, we're looking into the financial opportunity all the way to the bottom line. I'm going to update you on the model excluding HMI that we introduced two years ago. You'll see that it has some small changes, it literally reconfirms the 10 billion revenue opportunity, and an EPS associated with it, of about a little bit over EUR 8. I think that's very consistent with what we said before.
You have just heard Christophe describing the market, going from qualification to monitoring and control adding a little bit of an opportunity for mask inspection. There's a EUR 2.5 billion additional market that we can address over time. We believe that that will translate both from existing HMI products and the products we will create together with them in the pattern fidelity metrology space, another revenue opportunity of EUR 1 billion. We're going to increase the model to EUR 11 billion in 2020. It will be accretive to the gross margin because this is a software and hardware business. We believe the earnings per share opportunity will be greater than EUR 9 per year. Then I'm going to finish off with our capital allocation model. Also there, no major change. I believe what we have done has been working.
Of course, we are going to apply significantly higher free cash flow numbers in the future to it, which are a result of the financial model. With that, I'd like to just use three charts to talk about the past. We're a technology leadership company. We have invested very significantly in technology over the last couple of years, to create value for our customers. If you just take R&D and CapEx, we have increased that number as you go back to 2012, by a 16% CAGR. Having said that, we have stabilized the number over the last three years. There we are talking about EUR 1.1 billion, approximately in R&D. We supplement this with very strategic acquisitions where we believe we can really add industrial value.
Cymer, of course, was needed to make progress on the light source Christophe just explained HMI will put us in a position to create entirely new products for the customer. I want to point out two extra items here, I think that is important. On the R&D, I have split out for you EUV and non-EUV. Sometimes we talk a lot about just EUV, I want to make clear that everybody understands that we are spending more than half of our R&D investments in DUV, fundamental research, holistic lithography. It's the cash cow. It has significant growth associated with it. You saw the roadmaps. There are ongoing investments. There are products under investigation. We're investing heavily in all of our product lines.
The second point I want to make on this chart is if you look at the top of the stack, CapEx, you will see that our CapEx year-over-year has come down by about 20%. We were about EUR 370 million last year. We're going to be about EUR 290 million this year. There's also a preview in our model. We're going to slightly adjust what we're going to do on CapEx because the factories for EUV are pretty much done. Our CapEx has been coming down. Looking at revenue. This is a pretty nice, smooth revenue growth curve for the last five years, 9% CAGR. You will have all noticed that the CAGR has been driven by our installed base revenue. That's probably the term we are going to use in the future instead of services and field options.
The revenue is driven by our installed base has grown by 24%. Some of that was not quite organic. As you know, we've bought Cymer. There was a service model that came attached to it. A lot of it is driven also by the high-value upgrades that we're doing in the field. You saw that in some of my colleagues' charts, that all of our roadmaps are also enabling upgrades going forward. Gross margin. We're making progress. You see that we are slowly creeping up, but we have a reduction in gross margin in 2016. This is entirely driven by increasing EUV revenues. To make this perfectly clear, I want to give you a number, and I'm going to discuss that number later on.
The gross margin of EUV this year, if you count everything, we are going away from the standard costing accounting term to counting everything that impacts the EUV business, all the cost of under absorption, E&O cost, excess and obsolete, and so forth. The gross margin of the EUV businesses this year on about EUR 300 million to EUR 350 million revenue is minus 75%. I'll show you later on how we're going to get this to 40% and beyond over the next couple of years. The point I want to make at this time is if you do the reverse math on the numbers that I just gave you, that our DUV and our holistic lithography businesses have highly attractive margins, plus a future opportunity while delivering value to the customer.
You can do the math by yourself, but you'll find out that with these numbers, these businesses are north of 50%, around 52% for the current year. Having done all this, I won't spend much time on this. You're the judge on that. We believe that we have significant growth left, but in the meantime, we have done okay versus Nasdaq in stock price appreciation, and we're also getting back later on to the capital allocation strategy. We have progressively increased our dividend to add to the total shareholder return, and last year, we made a step function by 50%, and that's also going to be, going forward, our objective to continuously increase the dividend, and I'll get back to that as we progress through the presentation. That's a quick look back to the numbers. With that, I would like to focus more on the future.
The first chart I'm using is essentially the same chart that Peter had in his presentation as well. When our business lines and marketing and market forecasting experts look at the market, they start with the end users. Peter talked about all the different things in mobility, cars, Internet of Things, servers, et cetera, that will drive the end markets up. For us, we translate it first into wafer capacity. I don't go into all the end users, but you can see from a pure wafer capacity perspective, all of these markets, logic, performance memory, and storage memory, will require more wafers over time. Of course, for us, that is only one part of the equation. We get our systems revenue, A, from growing capacity, but B, from node transitions and increasing litho intensity that comes with these node transitions.
That's why I want to show you this second chart here, which is a bit more busy, so I want to introduce it to you. Basically, you have The three areas of usage of our technology, logic performance and storage memory. You see in the middle section how a typical factory will be equipped with lithography tools for a given number of wafers that you want to process in the factory. For logic, for instance, it would be 45,000 wafer starts. For performance, 100,000. That's just a typical footprint that you use. In the middle section, you see what kind of tools you need for that capacity. The legend at the bottom shows you what's EUV, what's ArFi and so forth. You can see that for all three technologies, there are more little boxes as we move forward.
For all three technologies, you see ArFi and EUV increasing. This comes back to Hans' numbers, what you need approximately at a given layer count and capacity. On the right side of the chart, you have it translated into EUR. You basically have expressed what the customer has to invest to get these wafers out at a given new technology. For instance, on logic, you see node over node, the litho intensity going up by 40%, performance memory 30%, and in storage memory, driven by stacking of stacks by about 20%. On that one, we chose to give you a little bit of a tail of the curve, because in that study period, it doesn't include yet the new memory technologies such as 3D XPoint, ReRAM, and so forth.
I want to give you a preview that will be also a significant litho intensity increase as we move forward. Well, I show you this chart really quickly because we are, also to Peter's point, always obliged to check that litho intensity, whether it still makes sense for our customers to make that investment. With that litho intensity increase you see in the blue line going down, we believe that we can stay pretty close to Moore's Law in terms of cost reduction per function. It's at 21% per year. Every two years, if you compound it, you get pretty close to the 40%-50% range. With that increase in litho intensity, we are able to continue to deliver the value to our customers. Now I want to go into a little bit more details on how we model 2020.
For that, I want to share with you a few assumptions. Again, now on the top in the columns, the three areas, the three markets that we serve. Some general assumptions. On market share, I think the one that we can't argue is EUV at 100%. There's nobody else there. We have modeled about 80% in immersion and about 50% in dry. In general, we have looked at EUV insertions in line with the quotes that you have heard from my colleagues. 2018, 2019 for logic and performance memory, and storage memory is going to be in 2020, so you'll probably see a few tools before the end of the decade. In terms of market growth, again, for logic, we projected the wafer starts per month.
We think that a higher market would be represented by flat wafer starts per month, we're starting with 1,614 at about 270,000 per month. In a very depressed market, that could be going down by 20%. That's not what we're forecasting. We just did it for simulation purposes. For performance memory, we just varied the bit growth between 20%-30%. For storage memory, we have chosen 40%-50% because we believe, based on Martin's chart on the different storage technologies, that indeed, semiconductor-based storage will eat into rotating memory over the next couple of year, and will take the bit growth up there. Last but not least, we took the intensity of the EUV insertion, how many layers or exposures will be done in the different end markets. I don't want to repeat the numbers. They match with what Hans said.
If you apply these numbers, you're going to get to a similar chart that we showed you in 2014. I sensitized around these two vectors, market demand and EUV insertion, if we focus on left first. If you vary the market demand and do it based on an average layer count, you can see at high market demand and in low market demand that the revenue will be anywhere between EUR 13 billion and EUR 8 billion, if you round it up. Our expectation at this time, you can take your own, we believe is probably not going to be at flat wafer starts, but it's also not going to be 20% down based on all the different applications and uses. A moderate market growth would be somewhere in the middle of these two. Again, you would get somewhere north of EUR 10 billion.
If you do the same thing on the right side, you assume a moderate market, then you vary the exposures. You see at a high insertion rate, which quite frankly, if we get to the availability, our customers will be leaning towards because of all the value getting out there. We're getting to EUR 11 billion, and if it's a lower insertion rate, we compensate with more ArFi tools, but we would still get to EUR 9.5 billion. This is a couple of examples how we sensitize this. Based on that, we have a high level of confidence that in 2020, we will be able, without HMI contribution yet, to get to EUR 10 billion in revenue. Let's translate that all the way through the financial statement. Busy chart here.
Just give you for reference the 2014 actuals, the 2016 forecast with the guidance that we have provided on our call two weeks ago, and the prior model for 2020 that we have discussed in November of 2014. You see the EUR 10 billion there, the 50%. I want to highlight again, one major element of getting to the 50% was getting EUV to 40%, and I'll get back to that. R&D and SG&A will increase slightly in absolute terms, but as a % of revenue, they will be coming down to 13 and 4% respectively. 5% for CapEx. 200 days on the cash conversion cycle. We are currently operating around 280 days. That's mainly driven by inventory, and that is mainly driven by DUV. I should say, exclusively driven by DUV.
We have operated below 200 days before, and we believe we can get back there once EUV is more like a run rate product. Back then, we talked about a tax rate of 10%, approximately 10%, and as you all know, driven predominantly by the tax regulations in the Netherlands called the Innovation Box . Back then, we didn't provide an EPS number. We talked about tripling of earnings. No substantial change versus the model we provided a few years ago. We changed only three things. Number one, we took the CapEx down. You already saw the 2016 numbers from 5% to 4%. We have increased the tax from approximately 10% to 13%, which has to do with changes in tax laws. As a reminder here, this is the year where our current ruling for the Innovation Box in the Netherlands runs out.
The Dutch government is currently in the process of rolling out the law. We are in all the focus groups. We pretty much have a good insight on what's going to happen. We never know for sure, but based on what we know right now, there's not going to be any substantial change in the application of the Innovation Box going forward. We believe that the 13% should be okay-ish. Rather than telling you tripling, we're now saying it's greater than EUR 8. That's basically the natural evolution of our model pre-HMI. I want to get back to the -75% gross margin for a minute because that is a question we get asked a lot, rightfully so.
We have, in the past, talked more about where we are developing at a standard cost, but we believe it's more prudent to give you the overall gross margin of the business. Let me do this. Pretty simple. We go from -75% to 40%. Well, it looks like a bit dumb, but I haven't told you where we were in 2015. If you don't like where you are, it's always good looking at where you're coming from. Kidding aside, we do understand what needs to happen and what's happening naturally pretty well. There are four elements that I want to highlight on. The first one is if you look at 2016, what we shipped are 3350s. Of the 3350s, in some cases, we only had partial revenue recognition.
You're taking a product that is about EUR 95 million, then you're not recognizing the full revenue. As you go into the next year, we're going to ship 3400s. If you look at the roadmap carefully that my colleagues presented, there are potential enhancements of the products before 2020 that will add value to the customer. That's the first box, product mix and revenue recognition. The second one is Hans showed you these beautiful pictures of these factories. They're not full. The building is there, the depreciation is there, the factory management team is there, the lights are on, the utilities are on, people are there. We're going to absorb all of these costs over a handful of systems that we built this year. Next year, we're going to double.
If all goes well with the introduction 2018, 2019, we may double again, that is the second big effect. If the volume comes, we get that increase in gross margin automatically. The third point is cost. As usual, you need to go through your learning curves. It takes you X hours to put one of these systems together in our factory. In 2020, it's probably half X. The same applies to our suppliers, with that, you get the cost of the incoming material down. It's also X is an obsolete. When you develop a system like this, you have a component, you think it's right, when you get there, somebody comes up with a better mousetrap you're going to basically scrap material that you already had. It's pretty significant at this point in the program.
That's the third category, the fourth category is service margin optimization. We're going to change the model here a little bit like the Cymer light source model, where we charge for billion pulses. We're going to charge per good wafer out, which is good for our customers because it makes it all variable and they can easily attach numbers to it. At the time where we are right now, where there's almost no good wafers out, the crew is there, we have significantly negative gross margins in the service business, which is also hit by upgrades that we have to do in the field that we cannot charge for because we rolled out one version of the machine that needs some work that we cannot charge for.
It looks like a big difference between -75% and plus 40%, a lot of it comes with the rollout of the roadmap and with volume and getting that volume also translated into service gross margin. In terms of the EPS, I look at my time and I'm a little bit challenged, so I keep this short. The street estimate is EUR 3.24 for this year. If you apply the revenue increase without any more fixed cost going forward at the current gross margin provides you almost a doubling of that gross margin improvement continues to drive this up. OpEx, we're investing in, particular in R&D, will take a little bit back from the EPS.
We're executing our financial policy, which means that we are going to use the free cash flows generated by the business, use it for dividends, but also share buybacks as what we modeled here. Likely wrong because we took €96. It will be different, of course, going forward. That's how you see how we get to a tripling of the EPS. HMI. Quick status update versus our call two weeks ago. The only thing that has changed is a significant change. We got the two approvals that we were missing. We got the outbound approval for the private placement from the Taiwanese Investment Commission. We also got the Korean FTC approving the deal, which is significant in my mind. What remains outstanding is the delisting of HMI at the Taiwan Stock Exchange, which has been requested by HMI.
The request date was for the end of November. Last but not least, we have started exchanging dollars and euros into Taiwanese dollars because that's the currency that's in the purchase agreement. We're doing well here. Changes to the model. On the left side, the model without HMI that I just introduced. EUR 1 billion more in revenue, driven by the market opportunity Christophe highlighted. It's not just HMI products, it's also the new products that Christophe and Jack developed together. Gross margins will go up. This is a software and hardware business. Gross margins, you know HMI is about 70%, so it will be accretive to the gross margin model. In terms of R&D, SG&A, and CapEx, we have no significant change relative to revenue, how HMI is run, so that will stay the same. Tax rate will go up by one point.
It has to do with HMI's tax jurisdiction being Taiwan, where the corporate tax rate is about 20%, so it will take our tax rate up a bit. It will be nicely accretive at the bottom line at over €9 per share. Attractive financial model. You can do the math with the cash conversion cycle and CapEx reductions. It will lead to very significant free cash flows. With that, I'm coming to my last chart, and that is on continued shareholder value creation through capital allocation and other means. The long story short there is, we're planning to apply what has worked for the last couple of years, execute our financial policy here. Our top priority remains liquidity and financial stability. In order to do that, we, on an annual basis, establish a minimum gross cash balance that we want to keep in the bank. Currently, it's about EUR 2 billion-EUR 2.5 billion. On top of that, we have a revolving credit facility of EUR 700 million, so liquidity taken care of.
Currently, it's about EUR 2 billion-EUR 2.5 billion. On top of that, we have a revolving credit facility of EUR 700 million, so liquidity taken care of. We want to be investment grade so that we have access to the capital markets, for whatever reason. We're solidly investment grade with BBB+. Our leverage is about 1.5 even after financing HMI. We will consider M&A only where it makes clear industrial sense. You have seen that with Brion, you have seen this with Cymer, and you have also seen this with HMI. Whatever is left over, which should be substantial, we go in a two-step process. First step is to, every January, look at the dividend that we're giving back to shareholders. Our target is to keep it stable, preferably growing, which if you look at the bottom right, have been doing over the last couple of years.
Whatever is left, we're going to use to buy back our shares. Pretty consistent with what we have done in the past. I spare the summary slide, but decent business model in the past. The market is growing. I think it's a very attractive model going forward in 2020, and it will be good for all stakeholders, but it has a very attractive return strategy for shareholders as well. With that, I finish my piece and hand it back over to Peter for the wrap-up.
Thank you, Wolfgang. Yeah, it's going to be short. In fact, I hope when you've listened to us for the last two hours, or more than that, two and a half hours, you come to the same conclusions as we do. That shrink, in what form we talk about, is going to be a key driver that will support the innovation and support industry growth. That can take many forms, and Martin talked about this, but we strongly believe that lithography is a key element of this. Because it will provide affordable shrink, and it will provide value to our customers, and it will be particularly driven going forward by EUV. We will not forget our workhorse, Deep UV. It's going to be mix and match. EUV will enable this continuation of Moore's Law, not only for the next five years, but for the next decade also.
We will do this, like we said, with products, EUV and Deep UV, that we believe are unique. Particularly true for EUV, we will be the only one. Also for Deep UV, where we have solutions that are really unique and that provide the requisite value to our customers. Particularly important because, I hope it is also clear that the combination with holistic lithography provides the true value that customers are looking for, enabling them to control the ever-increasing absolute cost, but driving the cost per transistor down. It's particularly important that you see that we are becoming not only an imaging company, but that we are in fact a patterning company, and that the combination of our classical lithography systems, our metrology systems, and our holistic litho program is in fact one product offering to our customers. Now, we will do that. We will execute on this.
When we execute, and looking at the roadmaps of our customers, looking at the assessments we currently have on the end markets, it's clear to us that we comfortably can reconfirm our EUR 10 billion target for 2020, which will give us an over EUR 8 earnings per share number. However, like Wolfgang said a couple of minutes ago, the HMI acquisition will close, and that will add as a EUR 1 billion to our top line. We up it up to EUR 11 billion by 2020, and over EUR 9 per share. The world doesn't end in 2020. I think, I hope we've made it clear that there is so much we can still do. There are so many ideas to keep moving Moore's Law forward at affordable cost. That will bring the company in the next decade to the next growth level.
We've lifted the tip of the veil, over EUR 15 billion for systems, over EUR 5 billion for install base services. There is ample opportunity. When we do that, given our financial model, our financial policy, excess cash will return to the shareholders. We've done this in the past, you've seen the stats, and we'll keep doing that going forward. With that, I would like to conclude, and open up for questions and answers. Craig, you have something to mention?
Is this mic on? Is that good? Yeah, thanks. Thanks, Peter. Our challenge, we've dumped a lot on you here in a very short period of time. Our challenge was to be concise and clear. I hope we did that. I think everybody here largely understands our business and our business model. Our challenge today and our interest today was just to reinforce the opportunity and give you an update on the drivers of our opportunity. I hope we did that. I also, you guys, a lot of you have come a long way. I wanted to give you a chance to interact with management. We have two ways we're going to do that. We're going to reset the stage here, and bring the gentlemen back on stage so we can do an active and live broadcast of a Q&A session for about 30 minutes.
We didn't get a break. I invite you, if you need to leave the room, but come back as soon as possible because we do have people waiting out there somewhere listening to the webcast. We also, real quickly, have a treat for you. The gentlemen will come through the crowd here and offer you a treat. It ain't that much. No, actually, we have a treat here for you in these little buckets, and these treats contain all the presentations from the day. If one or two of them don't work, they came pretty cheap. Bad luck. They're pretty cheap, and that's your trick, I suppose. No, hopefully they'll all work for you. They're on there, and of course, this will be on the website in the next hour or so.
Take a break, take a stretch, make it short, grab a treat, and we'll see you back here in five or less if you can. Thanks. Thanks. Got it? There we go. Yeah, we're good. He got it. All right. Hey, can we have everybody come back in and sit down as fast as possible? Everybody, did everybody get a treat? Yeah? The little USBs. No? We'll get you one. Make sure you get one before you leave. Can we have everybody come on in? Skip? You going to get the people in if they're outside? We'll get this started as soon as we can. Again, to be efficient, get everybody maintain some schedule. While we're waiting for people to come back in, we've provided a modest little gift also for you, a little charger and a pen. Take that along with you, please.
I want to make sure everybody, before we start, did get a treat. If anybody didn't get a treat, which is a little pumpkin or a little ghost USB, could you put your hands up? On the bottom of those, by the way, before we start, real quickly, on the bottom of those, there's two that have a red dot and two that have a gold dot. On the bottom of the USBs, there's two and two. When we're done with the Q&A here, I'd like to give out another couple of tricks and treats. Look for a little red dot, a little yellow dot, and I'll be back to you on that. Do you guys want to come up on the stage, and we'll start the Q&A? We have three microphones throughout the audience here.
There'll be three gentlemen strategically placed throughout the room so we can handle questions for you, from you. Please, when you ask a question, if you could stand up so the gentleman up here and the rest of the crowd can see you. Not to embarrass you, but just to recognize you. I think we're waiting for-- Is Martin back? We lost Martin, I think. Which is not uncommon, by the way, but it is. Don't be afraid.
If anybody has a highly technical question, we'll just wait till Martin is here.
Yeah. I know there's at least one in the crowd, a highly technical question, someone just came up. Okay, I think we're ready to go. The mics are live up here on stage. If you have a question, right here we got microphones. Where are my microphones? Go ahead, Pete.
Hi, Carl Ackman on for Tamarac, [accounting] company. In order to achieve your 40% gross margin target in EUV, how many tools do you need to achieve that goal? In your low insertion and low demand model of 20-25 tools, what does the gross margin look like for EUV and for the overall business?
Okay. I can start this off. Is this live?
Live?
Microphone live?
Yeah, you're on.
Like you have seen, there is four major drivers for EUV gross margin to get to 40%. You can be in a situation where you are at 40 tools, and you're not delivering on the other three items, and you're below 40%. Vice versa, you can be at a lower volume, and you can still over-deliver on the other elements and still be at 40%. The message is you cannot pinpoint it to one specific number. You have seen from the numbers that we will be anywhere between around 40 tools or so, if you go just to the right side, where you have the high insertion with a moderate market. You should assume that with 40 tools, you get there, granted that everything else is delivered there as well. You could also have fewer tools and still get there.
I want to give you one additional data point that I wanted to mention also during the presentation, but I forgot, to give you an indication how we are making progress. Next year, 2017, we will have made progress on all of these four categories. We believe that we, in that case, will already be at gross margin breakeven. We believe next year we'll make a significant progress. We said before we are going to ship, have the capacity to do about a dozen tools, plus two tools that are rolling over from this year. You get a bit of a feeling how quickly it can go when the volume rolls in. On the second part of your question, at the bottom end of these models, the margin will be lower in EUV.
I don't think that it's going to be lower in holistic or DUV. In EUV, you would have less absorption, and it would be somewhat lower.
Yeah. It is clear, like Wolfgang said, as a big driver is, of course, volume, and you pointed to that point. Volume is a big driver. We have a big industrial base. We only got very low coverage this year, only effectively four system shipped, partially revenue recognized. All that cost is under-absorbed, which of course, when you move next year to 12 units plus, and the work we've also done on the other issues, like the excess and obsolete and like the product mix. We'll sell 3,400s next year, which has a purchase order price of EUR 120 million. That all helps, and it brings you, with those dozen or so units, brings you to around breakeven. If you go to 40, you can do the math relatively easy. 40% is not a huge stretch.
I think you need to move some of those mics forward because the people I think a lot of. Okay, thanks. Why don't you-
Are we done with the questions?
Yeah.
Yeah.
Please come here.
Okay.
Yeah. Just a quick clarification, maybe, Wolfgang, on what you just said. If I understand you correctly, this year, on EUR 300 million, EUR 400 million of EUV revenues, this negative gross margin of 75% is like the cost of, let's say in the region of EUR 300 million. The marginal gross margin contributed by the 12 tools you're going to ship next year is going to be in that region of EUR 300 million. I'm sorry, when it comes down to modeling revenue growth next year and impact on gross margin, that's the way we should be thinking about it, like a contribution margin into 25, 30.
You have to add to what Wolfgang said. There is this product mix, it's the sales price. Every sales price goes up. That's one. That's very clear. We have the cost of the upgrades. We ship 3300s, 3350s, which actually have to be brought to 3500 level. Those upgrades also hit the P&L this year. It's the combination. It's the combination of the four things that we talked about. That gives you the break-even.
Thank you for the clarification. Then I had just a quick question on your metrology projects, I mean projections. It feels like I'm trying to figure out whether you're going to take market share and reduce the addressable market of alternative technologies, in particular, like everybody playing in process, not necessarily in process control, but in process monitoring and optic tools. Also, specifically on HMI, is the technology going to replace actinic inspection for masks?
Well, I think the last question on actinic inspection, I leave to my left side, probably better equipped to answer that in detail. I think if you listen carefully to what Christophe said, we're creating a product that doesn't exist today. In fact, we are in fact creating a market of something that cannot be done today. We strongly believe that is additional. Whether that goes at the expense of somebody else, we don't know. As a matter of fact, it's the same thing when we introduced YieldStar. We in fact had this internal control loop, where you basically have an integrated control loop, was also new. It's a new market. We're trying to create something new, and we're not so much focused on trying to replace anybody else. We're trying to create value.
If we're good at it and we succeed, we believe customers will also recognize that value and buy that product.
To add a few statements. First of all, amplify what Peter is saying. We're not after somebody else. We're after solving the little problem and also allowing the little tool, as Christophe alluded, to correct some of the process correction. We're not here to ring the alarm bell in the fab. We're here to take that information as a feedback loop. On the actinic wavelength, at least for insiders, that could be a bit loaded question in the following sense. Actinic wavelength has been a dispute on EUV, actinic wavelength mask inspection. We believe, as been stated by those who did consider developing it, that there's no clear business case for actinic wavelength inspection on EUV, and therefore, the only solution there is using the mask inspection, making a wafer image, and inspect through multibeam E-beam inspection, the wafer defects, the imaging defects.
This will add structurally some cycle time to the mask making process, this is a solution. There, we're not replacing anything. We doing something which nobody yet has considered playing. At the same time, we believe the strategy of wafer-based mask inspection has high synergy with the wafer metrology, therefore, you can build an overall business case on both doing mask inspection through wafer inspection and the defect control process.
Sandeep.
Hi. On to the metrology question. When you acquired Cymer, you had to invest more into Cymer to be able to get them up. You scaled up the R&D effort into Cymer. In the same way with HMI, with need for multibeam, is there need to scale up to be able to create that inline tool that you plan to have in the feedback loop? Secondly, with regard to the EUR 200 million opportunity that you've talked about on the mask inspection itself, I saw one of the slides which suggested recently that Intel plans to use this mask inspection as such, really. That would be, in a way, share gain for you, for HMI from the existing mask inspection business. This would be with EUV. They would be a new supplier of mask inspection.
I'll take the first one of my colleagues can take the second one. Yes. Just to give you a feeling, HMI's annual R&D is somewhere in the mid-30s, EUR 35 million. We have in the business case, provided for additional investments on our existing business in the holistic lithography application side, also on the HMI side. You will almost not see that in the larger scheme of things. We have clearly planned for providing resources to accelerate that roadmap. It is going to be covered in 2020 by our 13% ceiling that we have seen right now.
Christophe can probably.
I think to repeat a little bit both Wolfgang and Martin comments. The whole acquisition of HMI is done with intention to come with new product. I would say to accelerate technology that has been already quite successful. We mentioned in the past that we worked already with HMI for a couple of years, and I think we are ready to really go and try to make use of this technology. I think some of you already mentioned some of the application. We talked about model, we talked about wafer inspection, reticle inspection. We want all of this, I would say, to be available, as soon as possible to support the lithography business. I think there was a question on multi-beam also. Multi-beam means more speed, which from our experience, when it comes to metrology, more speed is always a great thing.
This is definitely also something we would like to accelerate even further. That's also the kind of discussion we already have with the HMI team.
Let's also amplify that, Christophe. I think, somebody, the first question was, what do we do different in metrology than anybody else? We have been the first company driving productivity on metrology to the extreme. Significant amount of existing players in metrology was about shipping boxes, many boxes to customers, where we say, it would be more valuable for us and for our customers to drive productivity both on the optical side, which continue to exist, as well as the e-beam side. E-beam productivity, the only way you drive e-beam productivity, you go for multi-beam. We believe in high productive metrology, getting lots of data, allowing it to wafer density sampling, allowing the field-by-field exposure parameters, being able to correct for whatever goes wrong in the fab, for the simple reason, because we're the only tool who can do that, which are on that level of detail.
It's really the lithography in combination metrology driving the productivity metrology, not to sell less tools, but to do more effective metrology and therefore more effective correction.
Thank you. It's Mehdi Mostafavi from Susquehanna International. A couple of questions. One for Wolfgang. It's great to see that you're maintaining the EUR 10 billion revenue target for 2020. Your slide suggests that the mix is changing. If I remember correctly, last time you talked about worst case, best case EUV shipment of 40-60, and now, I think it was, 25-45. What has changed, and what are the key segments that are driving the lower EUV shipment? For Peter or others on the panel, you're talking about, maybe if I just assume it, reasonable growth rate for the industry. The HMI will give you a EUR 3 billion TAM, EUR 3 billion plus TAM. You're talking about a EUR 1 billion of incremental revenue just from HMI.
What gives you the confidence that you're going to be able to have a 30%-35% market share?
I'll answer the easy question first. No, I think the reason, Mehdi, is that what we just said. I think we are creating something that is not there. Yeah? I think that in itself, of course, will add to the TAM. This particular competence that Martin very clearly explained a couple of minutes ago, feeding it back into the scanner, tell me who else can do that. Yeah? I think that is an additional new market which will add to the TAM, which will probably be very much owned by us in that sense. We think, looking at it, we need to develop the product. The product needs to be accepted by the customer. It needs to provide a value that we are currently envisaging. A lot has to happen.
This is why we think it's a, you may call it a decent, a conservative or a moderate, but it's our view, at this moment, what we can do in that particular market. It's driven by the fact that we create something new.
inspection market. The question and what gives you the confidence is, given the current market environment, especially, it seems like the bigger M&A deals are not going to happen. What is it that gives you the confidence that execution will fall in place and incumbents will not come in with a different methodology? Yes, I agree with you. It's a different way of doing this.
Correct
especially considering the computational part of the approach. There are incumbents that could come in and create a roadblock. What I'm trying to ask you is, how you have thought about the incumbents that are in the market, and what gives you the confidence that you can overcome them and be able to convince your customers that a software approach is better than hardware-based inspection?
Well, Mehdi, it's both. It's not only software. It's of course both YieldStar, HMI, e-beam technology, plus the software. I think Christophe made it very clear in his statement. Is there 100% certainty of what we're doing? No.
Is there something of a dream there? Yes. Do we have dreams before? Yes. Were they successful? Yes. I think we have a kind of a history of making dreams come true.
Yeah. Very much so. Your questions are quite well up, and I do believe that this whole drive from us to e-beam comes in a moment where optics runs out, when it comes to lithography and also runs out on certain capability when it comes to metrology. The whole debate between optical metrology and e-beam technology is going on for quite some time, and we just have to see that the visibility of certain details using optical lithography runs out, of optical metrology runs out, and therefore we will see an overall shift to certain tasks going to e-beam. It will not kill optics because the optical metrology like YieldStar has a unique capability of getting a very high productivity, very cost-effective metrology. Where the optics will run short, we will just complement with e-beam and we'll complement the fast e-beam.
Not about having some kind of device which then has been highly accurate. No, we like to be very pragmatic and fast in getting a bigger picture of the chip. Now, will we be the only one doing this? I don't think so. You know who is playing in the market. There are other people also there in multibeam stuff. We'll see competition going on. We will not stop at just measuring the wafer. We will just continue connecting it to the computational litho and to the scanner, as well as calibrating our modeling, which is key of running a decent lithography process.
Let me touch on I think you still want to have your first question answered. Yeah, sure. Things change two years in. A couple of points. Number 1, EUV is later. It's about a year later than what we had assumed two years ago. Number 2, our assessment of different markets have changed. For instance, two years ago, we were thinking that new memory technologies would contribute to volume earlier, which they will but not by that 2020. You said probably a few R&D tools.
The last one is, you saw that we are investing more than half of our R&D into holistic solutions and DUV solutions, which will also put our customers in a position where they still can continue and use DUV, and they don't have to go to the very aggressive end of the layers that they're committing to EUV, which will follow later on once they have the availability in check. Having said all that, if you look at the scenario where when we get the availability done, then we'll gravitate to the higher end of what I showed and with a moderate market, I think you'll still get something around the 40 tool mark by 2020.
Thanks, gentlemen. I think over here. I had three questions, if that's okay, and hopefully they'll be fairly short. The first one was just on trying to square the commentary on the volume adoption of EUV, which you seem to have more certainty on the 2018 sort of time frame with the revenue guidance of by 2020. Does it mean that the EUR 10 billion number you could potentially achieve already in either 2018 or 2019 because that's when the volume insertion happens? Kind of reverse engineering that guidance, do we need kind of the next node to achieve the EUR 10 billion? Again, I'm just trying to square the kind of roadmap and the high confidence on the 2018 insertion with the overall frame on the guidance. The second question was on the EUV light source or on the lens.
I think Gigaphoton still exists and is doing R&D, is putting out press releases. Is there a chance that they gain any share in the EUV light source? Because I think in immersion, they have quite a meaningful share right now, and how would that potentially impact the ASP or the kind of revenue trajectory on those two? Thank you.
Well, on the first one, the volume numbers that we gave you and the roadmap, I think it's all focused on, I think it was Hans made that clear. Hans, it's the seven nanometer, we call the industry seven. That's basically the node at which we believe those volume numbers that we just gave you are based on. There's not a next node in there. We believe it's going to be a gradual adoption, like we said, I think Wolfgang said it, we will ship about a dozen units next year. We have a double of that capacity in 2018. There will be a gradual growth towards the 40, 45 units that he just mentioned.
On the source side. We enjoy multiple suppliers at the lithography systems, both Gigaphoton and Cymer. The economic impact of a source for a customer is such that we are taking the position that we will integrate the best source, and we also involve our customers there. That leads to the existing market share you have between Gigaphoton and Cymer. We continue to support both. On EUV, we had a major struggle prior to acquisition, both with Cymer and with Gigaphoton on making any substantial progress on sources. We have in the end, selected Cymer as being the best partner for us to develop the source, and we have added major funding and major resources to the team.
In fact, today, rough numbers, one third of the resources, only EUV resources are resident in San Diego and two third of the resources outside San Diego, to give you a perspective how big of a team it is. We have continued to monitor the progress of Gigaphoton, and we are all impressed by the progress. However, they have yet to show a complete integrated system. For instance, they have not integrated yet the collector, which is not showing up evidently from the press releases. As you know, the whole source work with tin droplets. Tin is the beauty of having a high conversion efficiency from the infrared light to EUV, but it has the other part of it, that it starts dropping tin on the collector, and reducing transmission as some of the slides of Hans show today.
That whole equilibrium between how you maintain a clean collector and how you scale up the source power of an integrated system still has to show at Gigaphoton, and we continue to look at their progress. Based on our own insights, it continued to be very tough.
Thanks. This is Gareth Jenkins from UBS. I'll sit back down if you don't mind. I've got a few questions for both. Just firstly, Peter, you just announced quite a radical shift in your services model to wafer pricing. I wondered whether you could give us a sense of why that timing is now. Is it just on EUV products or is it the wider portfolio? That's the first question. I'll come back on the others.
Yeah. Actually, you're correct. It started with EUV portfolio. We had a lot of discussions with our customers on service cost and service models. We were triggered, but also by the way the service model has actually improved the internal efficiency of a company, once you know that you're almost looking at a glass ceiling of what you can charge the customer and still want to make money, you have to do things different. I think at Cymer, it was referred to that, and the OMPLs program there was a good program, and it is still a good program, because it effectively gives the customer not, let's say, a charge for misery, but it's just a variable cost because there has to be some level of maintenance.
You give that challenge to your supplier and saying, "This is what I'm willing to pay per wafer, and you make sure that you organize yourselves as efficiently and as effectively possible to meet my targets." If you do that well, you just have a good business model. I think that was, given the difficulties in coming to an EUV service model, we came to this charge per wafer model. It was triggered by the Cymer OMPLs model, and customers liked it. Actually, I like it too, because like I said earlier, charging a customer for misery because the tool stops and you charge her for parts and people and you send them a bill, you walk away. That's different than when you say, "Listen, I take the responsibility. You pay me for a certain amount per wafer and leave it fully to us. Yeah.
We'll manage it." That was well-received. Now we have the first deep EUV customer that also wants to go to a model like that. I think it gives us an opportunity to really look more efficiently at our organization. Actually, it's learning from an acquisition. It's good.
I've got a couple more. Secondly, just on the industrialization of EUV, how does it compare to immersion at the same stage, putting the sort of delays in EUV behind us now? As we stand today, the industrialization, is it similar? Is it more challenging than you faced on immersion?
I think there are some similarities and there are differences. I think Martin can talk to the differences, I think the similarities are that indeed also with immersion, with TWINSCAN, when we first introduced TWINSCAN and we shipped the first TWINSCAN, I think the meantime between interrupts was like five minutes. When we shipped the first NXT, we shipped the NXT 125 wafers per hour, or it was 150. We did 50. Yeah. It took some time. It took, yeah, it was a few years to actually get there. In that sense, there are some similarities. It's just the industrialization of a very complex product. Martin can respond to that better than I can. As at some of the technical challenges that we currently see, we have never seen before, and nobody has. I think that probably adds to it.
The disruption of EUV is bigger than with immersion. When we had immersion, there were two elements, which could be even, say one element, is the induced immersion defects because of the water interaction with the process and the amount of water left behind. I still remember when we started doing immersion, we had thousands of defects per wafer. Today, we have a major customer escalation, and we have more than a few defects per wafer. We are a few defects down, which is a result of extensive cycles of learning with the immersion system, as well as with the resist suppliers who improved the phobicity of the resist surface, such that the amount of water defects or water-induced defects have minimized. It took us several years to do so. The synergy of the mask and the resist formulation with water-free dry was high.
Today, we do have
a significant more complex system. Our cycle time for improvement, cycle time of replacing a module and replacing a new module with the amount of time was substantially higher. It will take us probably longer to get to a perfect EUV machine than it would have taken us to immersion to get to the perfect machine. The other thing is that the resist formulation need to be different because the resist deals with different photons, where in immersion you still have the 193 photons dealing with the resist. Now you have a 30 nanometer photons, which has completely changed the resist formulation, where resist vendors making good progress but only start developing it when our users start acceptance of our machines, which is only a few years ago. The last thing is the mask infrastructure. The mask is completely different.
Is instead of a transmissive mask, a reflective mask. Your metrology tools are not working anymore. You need to have a different pellicle. The whole mask should need to be retooled. The suppliers of the mask should need to be retooled. That's probably the biggest infrastructure change, which is taking place as we speak.
I think Hans made that very clear, in his overview. Also where you saw the customer assessment of the 8, 9 major items that need to be resolved. I think 3 of them are green. They're just ready. The others are in development, but we're making good progress. Like I said, on the mask inspection, to Martin's point, there is still work to be done, but there are also solutions out there that we can pursue.
My last question, if I can. Would you like to jump?
Yeah, okay. Gareth, can we move it around one more?
Okay.
Out of respect for the agenda we set and the timing of the agenda and the people attending via the webcast, I'd like to have just maybe one more question. We'll go to Pete's mic back there. One more question real quickly, if you don't mind. Just remind you, we're going to have a session over in the other room here, where we'll serve something to eat, and you can interact with these guys. They'll be available at least until 1:00 P.M. or 1:15 P.M. Feel free to do that. Apologize. Lots of questions. Sorry, we're going to just have to cut it short here in the webcast. Pete, if we can have one more question there, and then I'll be back in a sec after you.
Thanks for taking the question. Just a quick one. Can you help us understand what is modeled in HMI with regard to memory, and where do you see the opportunity for HMI as we go to the multiple layers of 3D NAND or DRAM into 1X or 1Y? Thank you.
Yeah. I think I showed you one slide during the presentation referring to voltage contrast. Voltage contrast is today, I think, the vast majority of HMI business. The reason for that is if you look at 3D NAND or if you look at high aspect ratio DRAM stack, there's no real other metrology way to look for yield issue. This, we believe, will continue to be true. As we did with other metrology system, the hope of course is to use this information to basically control also a bit more the process on those devices. I think we see that growing. In fact, we see that growing quite a bit, even on the short term, because I think as you know, the 3D NAND customer are planning to ramp quite aggressively in the coming years. We know it's needed for DRAM.
I think Martin showed a nice slide about logic, where there also we see a trend towards 3D integration. Voltage contrast I think is an interesting opportunity. To be honest, it's maybe one opportunity we are less familiar with still in ASML. That's definitely something we see as very important moving forward.
Very good. With that, we're going to wrap this thing up, close it up. On behalf of these guys and the extended Board of Management of ASML, we really want to thank you for coming and listening in. Again, we'll be adjourning to the room here momentarily. I'm going to ask everybody here to stay in the room just for a few moments, and we'll sign off of the webcast. Again, thank you very much. We hope we've informed you adequately, sufficiently on our opportunity. These materials, we hope, will provide fodder for discussion with management and the IR team going forward. Again, just thanks for being with us and see you next time. Thanks.
Great.