Good morning, good afternoon, or good evening, depending upon where you are in the world, and welcome to today's webinar, Breaking the AI Infrastructure Power Wall, Navitas 2.0 Completes the Grid-to-XPU Power Portfolio with Claros Acquisition, brought to you by EE Times, Navitas, and broadcast by AspenCore. I'm Colleen Heckman, and I'll be your moderator today. Today's webinar is a panel-style discussion. While we do encourage attendees to ask questions throughout the panel, please note that all questions will be addressed offline and directly. Just simply type your question into the Q&A text area and hit the submit button. If you experience any technical problems during the webinar, just type your issue into that same Q&A text area and hit the submit button. We'll be glad to offer you one-on-one assistance. Now, onto the webinar, Breaking the AI Infrastructure Power Wall.
On today's panel, we have Chris Allexandre, President and CEO of Navitas Semiconductor. Chris joined Navitas as President and CEO and board member in 2025. Chris is a seasoned semiconductor executive with over two decades of global leadership experience across sales, marketing, operations, and business unit management. He's held senior executive roles at leading semiconductor companies, including Texas Instruments, Fairchild, onsemi, NXP, IDT, and Renesas Electronics. Joining Chris today is Llew Vaughan-Edmunds, Chief Marketing Officer at Navitas Semiconductor. Llew is leading the company's global marketing organization while driving strategic initiatives across corporate strategy, business development, and M&A. Llew brings more than 25 years of leadership experience in global semiconductor industry, having held senior roles at Infineon, International Rectifier, onsemi, and Applied Materials. Finally, our third panelist is Dan Kultran, VP and GM, IVR Business Unit at Navitas Semiconductor.
Dan is the VP and General Manager of Navitas' IVR Business Unit and is former CEO and founder of Claros. Previously serving as the Chief Technology Officer at Epirus, he contributed to the development of systems addressing modern challenges such as asymmetrical technologies and drones. It's with great pleasure I now am going to toss things over to the Navitas headquarters, where the gentlemen are standing by. Gentlemen, take it away.
Welcome, and thank you for joining us today to this Breaking the AI Infrastructure Power Wall webcast. As you surely know, we have closed the Claros acquisition, and this marks a defining step in the Navitas 2.0 transformation. Why does it matter? Power has become a bottleneck for AI compute. Delivering more usable power, more efficiently is an enabler of more compute output. There is a direct link now between power efficiency and compute capacity. In today's webcast, I'm with Llew, our Chief Marketing Officer, as well as Dan, ex-CEO founder of Claros, and now VP and GM of the newly created IVR business unit of Navitas. We will cover and explain the power wall, the architectural changes needed to break it, and how Claros completes our technology portfolio. Let me do a brief disclaimer.
Our discussion includes forward-looking statements about our market, technology roadmap, and the expected benefits of the Claros acquisition. This reflects our current expectation and are subject to risk and uncertainty. Please review the disclaimer and the risk described in our SEC filing. Before we get going and go through the presentation, I want to share my excitement in joining forces with Claros and welcome again the entire Claros team to Navitas. As mentioned earlier, this is a very important step in our Navitas 2.0 transformation journey. This is more than just a portfolio addition. Claros connects our existing GaN and SiC capabilities with the critical final stage of power delivery to the processor. Those are complementary technologies. GaN and SiC address conversion and distribution across the higher voltage power chain. Claros brings integrated high-density regulation close to the XPU. We have one single system-level objective.
As the hyperscalers take more and more ownership of the full power chain from grid to XPU, we are now able to serve the entire need with one system-level objective, reduce losses and power density constraint across the chain so that more power can support more AI compute. We think grid-to-XPU really describe well the breadth of our combined portfolio in power and the customer problem we are addressing. Let us start with Navitas 2.0, which we started about a year ago. This is strategic shift away and deliberate pivot from consumer market towards high-power application with AI infrastructure at the center. As a matter of fact, as you might have seen from our past earning release, we expect mobile to be insignificant by the end of 2026, and almost all revenue to come from high power already. Essentially, this means the pivot has happened.
We focus on four markets, AI data center, grid and energy infrastructure, high-performance computing, and industrial electrification. AI infrastructure includes both data center and the energy system supporting, and this is really where the company is heading. We have three technology pillars, GaN for fast, efficient conversion, high voltage and ultra-high voltage SiC for demanding high voltage and high power application, and now Claros IVR for highly integrated power delivery to the processor. Our roots go back to strong technology innovation, as outlined by the number of patents now surpassing 450. This will continue, as well as our strong legacy with over 350 million units shipped. We remain focused on execution and scaling. Our operational priorities continue to be focused on strong and reliable U.S.-based manufacturing and supply chain, supported by our foundry plus model and strategic partnerships that we have announced.
We remain focused on strengthening the financial model through revenue scale, margin expansion and progress towards profitability. As commented at the announcement a few weeks ago, Claros acquisition does not materially change our plan for break-even point. Now that we have integrated Claros, let us review our SAM and long-term opportunity, which is much larger. Our identified 2030 SAM expand from the original $3.5 billion GaN and SiC base to more than $8 billion, including new JFET technology and Claros IVR. We have announced a new JFET product back last summer. What is expanding the market? Approximately $1 billion come from SiC JFET technology, and at least $3.5 billion from the VPD and the IVR opportunity. As you can see, AI infrastructure dominates with more than $6.9 billion and nearly 85% of our SAM, explaining why we outline this as the core focus of the company.
High-performance computing and industrial electrification remains important, but most of these opportunities align directly with our AI infrastructure focus. This is the addressable market, not revenue guidance, but it outlines we are in the right market with the right technology. Our task is now to translate this product portfolio into customer adoption and sustainable growth. Before getting Llew and Dan to go through the details, I want to show you what grid-to-xPU really mean and the overall power AI infrastructure, the architecture coming up. Read the diagram left to right. There are three essential jobs, bring power from the grid to an 800-volt DC infrastructure, convert it efficiently inside the data center, and regulate precisely at the processor at super high current. Grid to 800-volt DC, solid state transformers, battery storage, and power conversion system support efficiency, power density, resilience, and bi-directional energy flow.
Inside the data center, high-density DC-DC conversion steps power down towards the lower voltage rail needed by compute tray, while the 800-volt bus supports distribution. The final step, package and embedded IVR brings power down towards the 0.7 volt processor core, where high current and rapid load change makes delivery essentially demanding. All this together brings one system benefit, higher efficiency, fewer conversion stages, and greater power density. The value comes from improving the whole chain, not just one conversion point. As we discussed earlier, this directly impacts the amount of compute. Now to Llew.
Thanks, Chris. This slide really sets up the problem we are trying to solve. We call it the AI infrastructure power wall. It is a series of compounding challenges from conversion losses and thermal constraints to power density limitations, all the way from the grid to the processor. If we look at today's AI data center power architecture, from left to right, there are challenges developing at every stage. First, we start with traditional line frequency transformers. These have been in existence for over 140 years. They are bulky, heavy, and increasingly incompatible with the power density demanded by modern AI infrastructure. As data center power requirements move into hundreds of megawatts and ultimately gigawatts, the industry needs a much more efficient and scalable way of bringing power from the grid into the data center. Then we move into the AC to DC power supplies.
These convert the AC power to 48 volts DC into the rack. A s the AI rack power continues to increase, these power supplies are reaching practical limits in terms of power density, efficiency, and thermal performance. The next challenge is power distribution. At relatively low voltages, such as 48 volts, delivering more power requires dramatically higher current. As rack power increases, the current flowing through the system quickly becomes enormous, driving significant I squared R losses, heat generation, and the need for impractically large amounts of copper. We see the same issue inside the compute tray. Power still has to be converted from the 48 volts down to 12 volts through an intermediate bus converter or an IBC. This additional DC to DC conversion stage introduces power losses, heat, and additional components that consume valuable board space.
Finally, we reach what is becoming perhaps the most significant power delivery challenge, is the processor itself. Whether that's a GPU, a CPU, a TPU, or even a custom accelerator, these processors are consuming dramatically more power and demanding thousands of amps at sub -1 volt. When we talk about the AI infrastructure power wall, it isn't a single bottleneck. It's a cumulative effect of limitations across the entire power delivery chain. From the grid to the processor, legacy architectures are becoming pushed beyond what they are designed to support, creating compounding losses, thermal constraints, and power density limitations. As AI power continues to scale, simply improving each stage incrementally is no longer enough. We need to fundamentally rethink the power architecture from the grid all the way to the processor to break through these power walls and enable the next generation of AI compute.
The question becomes, how do we redesign the architecture to break through each of these power walls? This slide shows how we see the architecture evolving and how Navitas is breaking through the AI infrastructure power wall. The fundamental change is the transition to 800 volt distribution, fewer conversion stages, and dramatically higher power density across the entire architecture. Starting at the grid, solid state transformers, or SSTs, can replace traditional line frequency transformers, providing a much compact, efficient, and intelligent approach to power conversion. These SSTs convert grid power directly to 800 volt DC while enabling bidirectional power flow, active power management, and seamless integration with battery energy storage systems, improving both power density and the resilience of the AI data center. Navitas' ultra-high voltage silicon carbide technology enables the high voltage, the high frequency power conversion required by these next generation SST architectures.
At the next stage, increasing rack power is driving a transition towards much higher power density, requiring three-phase AC to DC power supplies. This allows significantly more power to be delivered to each rack while improving efficiency, power density, and thermal performance. Our high voltage silicon carbide MOSFETs support these higher power architectures with efficiency, switching performance, and reliability required for next generation power supplies. One of the biggest architectural changes is a move away from distributing 48 volts DC through the back plane to the individual IT trays. Instead, AC to DC and DC to DC power conversion moves into a power sidecar dedicated to supporting high power IT racks exceeding 1 MW, with 800 volt DC distributed directly to the rack and compute trays directly.
This higher distribution voltage allows significantly more power to be delivered while keeping current at practical levels, reducing I squared R losses, heat, and the amount of copper required in the back plane. At this stage, high voltage silicon carbide and medium voltage gallium nitride become key technologies, delivering the efficiency, switching performance, and power density required for these next generation architectures. The next step is the 800 volt native compute tray. Now we can bring that higher voltage much closer to the processor and use very high density, high frequency DC to DC conversion close to where the power is actually consumed. Navitas recently collaborated with NVIDIA to demonstrate 800 volt to 6 volt and 800 volt to 12 volt DC to DC power delivery boards that eliminate the traditional 48 volt IBC stage. Now this improves system efficiency, reliability, cost, and compute density.
Our high voltage and medium voltage gallium nitride FETs and GaN power ICs are ideally suited to this architecture, with a high frequency switching capability enabling smaller, more efficient, and significantly higher power density conversion directly within the compute tray. Finally, we get to the last few millimeters and perhaps the most critical stage of a power delivery. This is where vertical power delivery and embedded power delivery enabled by Claros' IVR technology fundamentally changes how we power the processor. In summary, the result is a fundamentally different grid-to-xPU architecture, higher voltage, fewer conversion stages, and higher power density. Together, Navitas' SiC, GaN, and Claros' IVR technologies address the power bottlenecks at every stage, breaking through the power wall and enabling AI compute to continue scaling.
Now, let's take a closer look at the processor power roadmap and why power demand is rapidly outpacing the ability of today's power delivery architectures to support it. This chart really illustrates the magnitude of the challenge. We're seeing an extraordinary increase in the power required by next generation AI processors. The trend here in processor power grows from around 1.4 kW in 2025, then over tripling to 4.4 kW in 2028 and heading to well above 10 kW in the next years. We're talking about an order of magnitude change in processor power over a relatively short period of time. Because these processors operate at less than one volt, supplying that power means delivering thousands of amps. It also means responding to very rapid changes in current as the processor moves between workloads.
The higher voltage distribution we just discussed helps us bring more power into the rack and compute tray efficiently, but we still have to get that power through the final stage and into the processor itself. There are three broader constraints behind the power wall shown on the right. First, we simply can't rely on Moore's law and transistor miniaturization to solve the problem. Improvements in the processor itself have to be matched by improvements in how we power it. Second, transmission and conversion efficiency become much more important at these current levels. Even small inefficiencies matter when we're delivering thousands of amps, making the final few inches of power delivery exceptionally critical. Third, packaging and thermal management have to keep pace. We need to deliver more power within a limited physical footprint while still being able to cool the system effectively.
Together, these constraints mean that having enough power available at the rack doesn't guarantee we can deliver it effectively to the processor. Power delivery itself is becoming a fundamental constraint on the next generation of AI compute. The key message is straightforward. If we want AI compute to continue scaling, our ability to power our processors has to scale with it. Dan will now take you to a closer look at that final delivery challenge and how Claros technology addresses it. Over to you, Dan.
Thanks, Llew. Let me double-click on that final delivery challenge and explain why it becomes so difficult at these current levels. Today, voltage regulators typically sit beside the processor, so the current has to travel across the board to reach the chip. As you just showed, we are asking that path to carry thousands of amps. That creates three challenges you see on this slide. First, electrical losses. At these currents, even a very small amount of resistance matters, and because resistive losses increase with the square of the current, doubling the current means four times the loss in the same path. As this slide highlights, lateral power delivery can lose up to 30% of the power that never reaches the processor. Second, these losses become heat. We are already trying to cool a very demanding hot processor, and now its power delivery system adds another thermal load.
That makes cooling more complex and uses part of the system's thermal budget that could otherwise support more compute. Third, the board space. You can see in the picture how much space the voltage regulators occupy around the processor. As current demand grows, adding more power circuitry puts even more pressure on the limited space. Building on your point, this is why the final few inches matter so much. We need to shorten the current path and make power conversion more compact. That is the challenge Claros IVR technology stack is built to address. Let me show you how we bring that conversion closer to the processor. Let us talk a little bit about that next-generation power delivery architecture. The first step on the left-hand side is vertical power delivery, or VPD. This is already starting to happen as compute density increases.
Instead of placing voltage regulators beside the processor, we move them directly underneath it on the backside of the board. Think of it as shortening the delivery path from centimeters to millimeters. A shorter path means less resistance, less energy loss as heat, and less parasitic inductance. That last point I made about inductance matters because AI workloads can change power demand very quickly. Lowering the inductance help the regulator respond faster to those changes and keep the processor running in a stable manner. The next step is embedded power delivery, or EPD. Here, we bring power conversion into the processor package or the substrate itself, further shortening the delivery path. We see EPD as the long-term destination for XPU power delivery. VPD gets us closer today, and EPD takes integration further as processor architectures evolve. Our IVR technology stack is designed to support both.
Moving the regulator underneath the processor through VPD and EPD is an important step, but how we build that regulator matters just as much. Many early VPD implementations take the familiar components from lateral power delivery, the power transistor, discrete capacitors, and inductors, and assemble them into a module underneath the processor. That improves the delivery path, but the module can still be very bulky and the power still have to travel laterally. As power demand keeps increasing, simply rearranging those components only takes us so far. That is why we have spent years developing the Claros IVR technology stack. We designed the digital control, power transistors, high-density capacitors, high-power embeddable inductors, and packaging all together as one integrated solution. That lets us optimize how they work together and how much space they need. The controller coordinates power delivery and current sharing. The power devices perform the conversion.
The integrated passive and advanced packaging help make the solution extremely compact and thin. This is the technology stack now we are unveiling as part of Navitas. Let me show you how it translates into products for both vertical and embedded power delivery architectures. On the left is Claros IVR technology stack, as we just discussed. In the middle are the two power delivery architectures, and on the right are the products that support them. The first is packaged IVR, or Navitas P-IVR. Think of it as an integrated IVR chip that can sit underneath the processor, replacing the larger modules I mentioned earlier. By integrating all the passive elements needed into our package, we can deliver more amps per given area. That true higher current density is especially valuable when space underneath the processor is limited. The second product is embedded IVR, or Navitas E-IVR.
Here, we integrate silicon chiplets and advanced passive directly into the processor substrate. That brings conversion even closer and creates a path to support much higher current level. We develop both products because customers need improvements before embedded architectures are ready. Package IVR gives our customers a way to adopt our technology sooner, while embedded IVR supports deeper integration over time. Both of these are built on the same underlying Claros IVR technology stack. Having a great technology stack is not enough. Let us look at how we build a platform to scale. We start with a repeatable 10 amp building block. We can combine four of those building blocks into a 40 amp chip, or 16 into 160 amp chip. To illustrate compactness, our 40 amp chip, which fully integrates all passive elements, measures just 3.3 by 3.6 mm, delivering over 3.4 amp per millimeter square.
Then we scale again by combining chips to meet the processor's total current requirement. The examples here show 64 chips delivering approximately 2,500 amps using the 40 amp configuration, or roughly 10,000 amps with the 160 amp configuration. T here are two levels of scalability, how many building blocks we put into a single chip, and how many chips we combine at the system level. This system level technology is called PowerArray. Our PowerArray technology uses an integrated digital controller, which coordinates the chips and manages how they share the load. That modular approach support both package and embedded power delivery architecture. We can build on the same foundation and configure it for different processors as their power requirement grows. Let us bring it all together.
The Claros IVR technology gives us an integrated platform for delivering power closer to the processor with products for both vertical and embedded power delivery. For customers, the benefits are straightforward, more current and less space, faster response as workloads change, and an architecture that can scale with increasing power demands. Together with Navitas gallium nitride, high and ultra-high voltage silicon carbide technologies, this extends our power platform from the grid all the way to the XPU. Llew, you showed us how we can improve power delivery into the rack. What I have just covered is how we carry that improvement through the last few inches to the processor itself. As AI grows, we see a significant opportunity to help customers turn more of their valuable power into useful compute. With that, I will hand it over to Chris.
Thank you, Llew and Dan, for detailing the problem we are trying to solve and how we plan to solve it with our Breaking the AI Infrastructure Power Wall strategy and grid-to-XPU portfolio. Let me recap and bring it back together. The AI infrastructure power conversion runs from the medium voltage grid through solid state transformers, high voltage DC distribution, and rack conversion to the low voltage processor core. Navitas' existing strengths, GaN and high voltage and ultra-high voltage SiC address the conversion and distribution stage leaning towards the compute system. Claros adds the last step, IVR address the critical final conversion regulation stage, enabling package and embedded approach close to the XPU. Complementary but not redundant. Higher voltage distribution and ultra-high current processor delivery are different problems requiring complementary technologies, but overall in the same system.
This combination strengthened our ability to engage with hyperscalers and AI power platform across the power architecture. As closing, I want to bring it back to one slide we already shown in the last earning, how those power architecture leads to dollar content increase and revenue scaling. Not one single transition. Our opportunity spans several architectural change. We are not waiting for every data center to adopt the final grid-to-core architecture. Number one, SiC in high power supplies. Higher rack power drives silicon to SiC replacement in high density AC to DC supplies, including system with approximately 50 volt output. Two, 800 volt power sidecars. Moving power shelves and battery backup into sidecars expands opportunities for SiC and GaN in conversion and power backup. Number three, the new AI factory architecture. Native 800 volt distribution into compute trays drive high GaN density conversion closer to the XPU.
Rising processors power also drive the opportunity for IVR that Dan explained. Solid state transformer. Direct conversion from medium voltage AC to 800 volt DC creates an opportunity for ultra-high voltage SiC in grid-to-core infrastructure. We expect opportunities for greater semiconductor content per system as these architecture evolve alongside the growth in AI infrastructure itself. With that, we want to thank you for joining us today. In simple closing words, the problem, power delivery and efficiency are becoming critical enablers to the next wave of AI compute. The Navitas 2.0 answer, a high power portfolio combining GaN, high voltage and ultra-high voltage SiC, and now Claros IVR grid-to-XPU. With Claros, we now address the critical final stage with an integrated scalable platform for vertical and embedded power delivery. Breaking the AI infrastructure power wall means turning better power delivery into more AI compute. Thank you.
T hank you, gentlemen, for an excellent and insightful panel discussion. To those audience members that asked a question, please note that we will address those offline after the webinar. For more information related to today's webinar, please visit any of the resource links located in your resource folder on your audience console. Within the next 24 hours, you will receive a personalized follow-up email with details and a link to today's presentation on demand.
T hank you again for attending today's webinar, Breaking the AI Infrastructure Power Wall, Navitas 2.0 completes the grid-to-XPU power portfolio with Claros acquisition. Again, brought to you by EE Times and Navitas. This webinar is copyright 2026 by AspenCore. The presentation materials are owned by or copyright by Navitas, and the individual speakers are solely responsible for their content and opinion. O n behalf of my guests and Navitas, I'm Colleen Heckman. Thank you for your time, and we hope you have a great day.