Good afternoon, and welcome to eMemory's second quarter 2026 Webcast Investor Conference. Joining us today is our Chairman, Dr. Charles Hsu; Head of IR, Ms. Li-Jeng Chen; Director of the Finance Department, Mr. Joseph Hsia; and Head of Digital Marketing, Dr. Felix Hsu. The format of today's event will be as follows. First, eMemory's Chairman, Dr. Charles Hsu, will give an opening remark. Afterwards, our Financial Officer, Mr. Joseph Hsia, will present a review of our financial results. Following that, Dr. Charles Hsu will share our business outlook. Next, Dr. Felix Hsu will give a talk titled, "Securing the Next Generation of AI Infrastructure, the Hardware Anchor for Caliptra Root of Trust to Secure Chiplets and Compute Express Link or CXL." Then we will conclude today's conference with the Q&A section, where our management team will answer your questions.
Please feel free to submit your questions in the input box on the webcast window throughout the conference. As a reminder, this conference is being recorded, and a webcast replay will be available after the conference is finished. For more information, please visit the company's website under the investor relations section. As usual, before we begin, we would like to remind everyone that today's presentation may contain forward-looking statements subject to risk factors associated with the semiconductor and IP business. Please refer to the cautionary statement on page 3 of today's presentation. Now, I would like to give the floor over to eMemory's Chairman, Dr. Charles Hsu.
Okay. Good afternoon, shareholders and investors. Welcome to our investor conference. First, I would like to report on our latest progress in the security IP. Over the past few years, our security IP has evolved from the foundational OTP and the PUF into a PUF root of trust. Today, as security requirements for AI servers continue to rise, our technology has taken a major step forward, advancing from a stand-alone security IP to the design of integration of comprehensive security subsystems. This transition is crucial for us. We are no longer providing clients with just OTP, PUF, or root of trust. We are now delivering fully integrated system-level security IP that combines encryption technology, software, firmware, and anti-tampering protections. In other words, our role within our clients' chips has become far more critical, allowing us to deliver significantly higher value.
Consequently, the potential license fee and also royalty are expected to increase significantly as well. We have a license to several major global memory manufacturers to integrate our security IP into SSD, solid-state disk, systems for AI data centers, providing the security subsystems required to comply with Caliptra standards. Beyond SSDs, we have also expanded into another vital area of AI servers, which is memory expansion IC. As AI model grows increasingly large, the memory capacity required by AI servers is surging rapidly. As a result, CXL is becoming a dominant interface technology for AI server memory expansion. CXL switch and their related controller chips similarly require a complete hardware security architectures. We are currently working with several CXL chip makers to supply both security IP and security subsystems. Connecting the dots over the past few years reveal a clear trajectory for our security IP applications.
Last year, we entered AI, AGI, CPUs, and also BMC. This year, we expand into AI data center solid-state disk security subsystems. Now we are penetrating CXL switch for the AI server memory expansions. This means our security IP is expanding from a single chip inside an AI server to multiple critical chip. Furthermore, many of these advanced chips are utilizing cutting-edge process nodes, such as 3 nanometer, and generating much higher licensing and royalties than corporate average. Another highly favorable trend for us is Caliptra. Driven jointly by global tech giants such as Microsoft, Google, Intel, AMD, and NVIDIA, we are seeing an increase in number of AI and data center chips and the system adopting the Caliptra security architecture. This indicates that the number of chip requiring root of trust security subsystem and the related security IP will grow significantly moving forward.
Therefore, we remain highly confident in the long-term growth of our security IP within the AI server and the data center markets. Next, I would like to also share some updates on another key growth driver we are heavily focused on, which we call the Logic Flash technologies. Currently, our collaboration with foundries on Logic Flash technology is accelerating applications extend beyond embedded flash to include standalone flash products as well. We believe the significance of Logic Flash goes far beyond adding another IP technology to our portfolios. More importantly, it presents an opportunity to leverage a more competitive process and cost structure to gradually replace portion of existing legacy flash technologies. Flash memory represents a massive market with exceptionally broad applications.
Once Logic Flash enters mass production and it begins progressively replacing conventional flash technologies, the market opportunity and the long-term impact on our future revenue and profitability will be far-reaching. For these reasons, we have a strong confidence in our multi-year growth outlook ahead. Next, I would like to invite our financial officer, Joseph, to present our second quarter performance. Thank you.
Good afternoon, everyone. Now let's begin with our 2026 second quarter financial results. The second quarter revenue was TWD 1,097 million, up 0.2% sequentially and up 17.1% year over year. Operating expenses were TWD 431 million, down 0.3% sequentially and up 10.2% year over year. In results, our operating income was TWD 666 million with an increase of 0.6% sequentially and an increase of 22% year over year. Operating margin also increased by 0.2 percentage points sequentially and increased by 2.4 percentage points year over year to 60.7%. Earning income amounting to TWD 580 million, experienced a decrease of 2.8% sequentially, but an increase of 44.9% year over year. The EPS for this quarter was TWD 7.77. Next, let's move on to revenue contributions by licensing and royalty.
First of all, licensing in the second quarter accounted for 39.2% of the total revenue, increasing 12.8% sequentially and up 35.1% year-over-year. On the USD basis, licensing grew by 12.8% quarter-over-quarter and 32.6% year-over-year. Royalty in the second quarter contributed 60.8% of our total revenue, decreasing 6.4% sequentially, but increasing 7.8% year-over-year. On USD basis, there was a 6.7% decrease quarter-over-quarter, but an increase of 8.6% year-over-year. Overall, the revenue increased by 0.2% quarter-over-quarter and up 17.1% year-over-year. On USD basis, the growth was 0.1% quarter-over-quarter and 16.9% year-over-year. For the first half of 2026, the licensing and royalty revenues are as follows. First of all, licensing in the first half accounted for 37% of our total revenue, increasing 45.2% year-over-year.
On USD basis, licensing grew by 45.9% year-over-year. Royalty in the first half contributed 63% of the total revenue, increasing 7% year-over-year. On the USD basis, there was 9.8% increase year-over-year. Together, the total revenue for the first half increased by 18.5% compared to the previous quarter, and on USD basis, the growth was even stronger at 20.9% year-over-year. With that, I will comment further on our revenue contribution by specific IPs. First of all, NeoBit accounted for 21.9% of total revenue in the second quarter. The licensing revenue increased 11.2% sequentially, but decreasing 22.4% year-over-year, while royalty increased by 9% sequentially and increasing 9.2% year-over-year. For NeoFuse technology, it accounted for 56.6% of the total revenue in the second quarter.
The licensing revenue was up by 24.8% sequentially and up by 55.6% year-over-year. In terms of royalty, NeoFuse royalty decreased by 13.3% sequentially, but increased by 4.4% year-over-year. For PUF-based security IPs, it contributed 10.9% of the total revenue. The licensing revenue decreased 13.8% sequentially, but increased 133.5% year-over-year. In terms of royalty, PUF-based royalty increased by 213.9% sequentially and increased by over 1,600% year-over-year. Lastly, for MTP technology, accounting for 10.6% of the total revenue in the second quarter. The licensing revenue increased by 40.2% sequentially and increased by 9.3% year-over-year. The royalty from MTP was up 7.2% sequentially and increased by 19.2% year-over-year. Together for the first half of 2026, the revenue by technology are as follows.
First of all, NeoBit licensing revenue decreased by 18.5% year-over-year, but the royalty increased by 2.4% and together accounting for 20.9% of the total revenue for the first half of 2026. For NeoFuse, the licensing revenue increased by 37.9%, and the royalty also increased by 6% year-over-year, contributing to 58.2% of our total revenue in the first half. For PUF-based security IPs, the licensing revenue increased by 264.6% year-over-year, and the royalty increased by over 1,300% year-over-year, and together accounting for 11.6% of our total revenue in the first half. Lastly, for MTP technology, the licensing revenue increased by 19.6%, and the royalty increased by 30.4% year-over-year, and together accounting for 9.3% of the total revenue. Now let's take a look at our royalties for 8 in and 12 in wafers.
First of all, 8 in wafers accounted for 37.5% of the royalties, up 4.2% sequentially and up 1.2% year-over-year. On a USD basis, this represents a sequential increase of 4% and a year-over-year increase of 3.1%. For 12 in wafers, it contributed 62.5% of the total royalties, down 11.9% sequentially, but increased 12.3% year-over-year. On a USD basis, this represents a sequential decrease of 12.1%, but a year-over-year increase of 12.2%. In total, 156 product tape-outs were completed in the second quarter, and we will provide more information in our management report, which will be released shortly after this earnings call. Next, I would like to invite our Chairman, Charles, to share a little bit more about our future outlook. Thank you.
Okay, in the following section, I will address our future outlook. As far as licensing revenue concerned, licensing will continue its strong momentum due to robust demand for our technologies from leading edge to the legacy process node, security and the next generation Flash technologies. For the royalty revenue, the royalty revenue growth is expected to accelerate as driven by the higher ASP from the new advanced node applications and the new application ramps, also expanding the PUF royalty contribution and a growing mix of higher royalty rate of MTP-related applications.
As far as new technologies, for the advanced node, OTP and the PUF-based hardware security continue to develop and qualify next generation OTP and the PUF-based hardware security solutions for 2 nanometer Gate-all-around technology and also sub 2 nanometer nodes and meeting growing customer demand in the device identity and key protections and secure boot and also hardware root of trust. Another new technology will be next generation 1T Flash. 1T NeoFlash technology is advancing across embedded also standalone applications and its logic processor-compatible architecture offers greater scalability, lower process complexity, and better cost efficiency. In the future, outlook for the business development platforms, which we have five items. The first is a chiplet security platform.
We continue to work with ecosystem partners on an end-to-end security framework for chiplet-based systems covering supply chain traceability, identity and authentication, also secure provisioning, also the die to die communication, also the key management and the hardware root of trust, addressing the increasingly complex security challenges of AI and also the advancing packaging and heterogeneous integration among today's geopolitical environments. Okay. The second item is the data center security and the Caliptra platform. Targeting the data center and the AI servers, we continue to upsell expanding PUF root of trust from a hardware root of trust solution into a Caliptra-compatible security subsystem and the integration service that reduce the integration complexity and accelerate customer deployments. Another business platform is on the AI compute and also root of trust platform.
We are extending collaboration across CPU, AI accelerator, and AI ASIC ecosystem to integrate chip level a root of trust, secure both device identity and also secure key protection into the next generation AI computing platform. Strengthen trust and also security from system into a system. From silicon to system. Another business platform we are developing is PUFhsm server and security-as-a-service platform. The PUF-based PUFhsm server combines device identity, key and certification management, and secure OTA updates, signature verification and the privacy protection and Post-Quantum Cryptography Migration. Early opportunities are progressing in the automotive, OTA, and PKI, and also HSM integration, with potential to expand it into the industrial control and the edge AI, smart device, medical, and also the data centers. The last platform, we call it Post-Quantum Security Platform.
We continue to strengthen our PUF-PQC portfolio with attack-resistant hardware security, including side-channel protection to support the transition to Post-Quantum Security Standards. Next, I would like to pass to Felix, our head of digital marketing to share with our feature topic today. Felix, please. Thank you.
Modern data centers depend on thousands of interconnected servers, each processing sensitive workloads, credentials, and proprietary data. System-level security ultimately begins much deeper inside the silicon. A server board contains chiplets of CPUs, accelerators, BMCs, networking, storage controllers, and other programmable devices. Each component loads firmware and communicates across shared interfaces, creating multiple points where trust must be established. Without a consistent hardware root of trust, compromised firmware, counterfeit components, leaked keys, or unauthenticated communication can allow an attacker to move across the board and persist below the operating system. Caliptra addresses this challenge with an open-source root-of-trust architecture designed for data center class silicon. It establishes a standardized security foundation that can be integrated into each major system on chip. During boot, the Caliptra subsystem begins from immutable code, authenticates its firmware, measures the device state, and derives protected identities and cryptographic keys
It can then support secure boot, signed firmware updates, and device attestations. However, the security architecture still requires a trustworthy physical source for device secrets, life cycle data, and entropy. PUFrt provides this silicon-level foundation directly beneath the Caliptra core. Its PUF generates a device-unique secret without permanently storing the key. OTP securely retains configuration and life cycle information, while the hardware noise source supplies high-quality entropy for cryptographic operations. With Caliptra deployed across critical devices, components can authenticate one another, verify firmware, establish protected channels, exchange keys, and produce evidence of their security state. The result is board-level security built from independently verifiable chips, extending a consistent chain of trust from each component across the server platform and throughout the data center.
EMemory and PUFsecurity, your trusted partner in providing non-volatile memory and PUF-based security intellectual properties.
Okay. Hi, everyone. What you have just viewed in this video is one part of a much bigger movement happening around Caliptra and the hardware root of security. Before I begin this talk, I like to briefly mention some related activities we've just been involved in. Earlier this week in Taipei, we participated in a Caliptra workshop focused on implementation and on bringing the specification closer to production silicon. We also presented at two sessions at OCP APAC, where we discussed Caliptra and chiplet security from both the architecture and systems perspective. Those discussions reinforce something we've been seeing more broadly across the industry. These security technologies are becoming increasingly important as AI servers and data center infrastructure become more distributed and more interconnected.
Rather than covering everything around Caliptra, I like to use the next few minutes to just focus on the underlying reason why this movement is gaining momentum. Instead of starting from security, I would actually like to start from how AI compute itself has been changing. AI systems are increasingly being built across multiple dies, accelerators, memory devices, and high-speed fabrics. As more components are connected together, more of these components and their interfaces also need to be individually trusted and protected. That's the story I like to present today. AI compute can no longer scale in a single die. When we talk about scaling AI compute, simply making chips larger is no longer enough. In the past, we wanted more performance, we could build a larger die or use more advanced process nodes.
But these are practical limits that we will approach, including die size, yield, cost, power, memory bandwidth, and IO all start to become constraints. Increasingly, the industry is scaling by composition. There are two important architectural trends shown on this slide, and I want to separate them because they're related, but they're not the same thing. The first one is chiplets, which operate inside the package. Instead of building one enormous monolithic SOC containing every function, we can divide the system into multiple specialized dies. For example, we have a CPU compute die, a GPU or NPU accelerator dies. We have management dies, a security die, or dies with other specialized functions. Importantly, these dies do not necessarily need to use the same process technology.
The compute portion may benefit the most from advanced node, but other dies, such as management, security functions, it may be more economical on less advanced nodes. Chiplets give us modularity, reuse, better economics, and another way to continue scaling the processor package. But even if we scale inside the package, we eventually hit another boundary, the processor socket and the server itself. That's where Compute Express Link, CXLs, come in. CXL operates at the system level outside the processor package. Here you can see the servers on the left connected through a CXL fabric switch to a CXL Type 3 memory shelf on the right. Instead of memory belonging permanently to one CPU socket, CXL allows memory and other devices to participate in a coherent fabric. That means memory can increasingly be expanded, pooled, shared, and dynamically assigned across systems.
You could think of it as chiplets scale the processor by combining multiple specialized dies in one package. Whereas CXL scales the system by connecting processors, accelerators, and memory across the server. That's a very important shift for the AI infrastructure. We are moving away from scaling only through one large piece of silicon and towards scaling by connecting many specialized resources together. But this composition has security consequences. Every new die link, device controller, and firmware layer creates another place where trust has to be established. That brings us to the next architecture. The same composability that gives us flexibility and scalability also creates a much larger attack surface. Let me separate this again to two architectural domains.
On the CXL side, we now have multiple endpoints joining a fabric, high-value memory, moving across links, switches controlling connectivity, and a fabric manager potentially deciding how pooled resources are located. That introduces several different classes of risk. For example, if the firmware of a highly privileged infrastructure component, such as a CXL switch, is compromised, the impact radius can be very large because now the attacker is not targeting only one endpoint. They may potentially manipulate connectivity, resource allocation, or the behavior of multiple devices in the fabric. Another important area is DMA, Direct Memory Access, which is in Panel 5. DMA itself is a legitimate and very powerful capability. The security problem is when a compromised or malicious device receives more access than it should have.
If those permissions are not properly controlled, a device can potentially read or modify memory outside its authorized region, and in an environment where memory is pooled or shared, the consequence can become especially serious. Data leakage across workloads or even between tenants. Inside the chiplet package, the security problem looks different, but the principle is the same. Now we're dealing with multiple active dies communicating across die-to-die interfaces. A counterfeit or rogue chiplet can introduce an unauthorized component into the package or supply chain, severely affecting silicon identity and supply chain trust. A malicious or unauthorized die can introduce hardware trojans, manipulate transactions, leak data, or undermine the assumptions of the entire package. Recent chiplet security research specifically highlights malicious chiplets and hardware trojans as major system-level threats. Chiplets may also be attacked, leading to key extraction and secret leakage, as shown in Panel 4.
If the root key or device secret is compromised, the consequence is much bigger than simply losing one piece of data. An attacker may be able to impersonate the device or undermine the trust relationship built on top of that identity. I don't expect everyone to remember these attacks, but the key point is the trust boundary has expanded. Security can no longer exist only at the board level or only around the CPU. What we increasingly need to know is this: Is the device or die authentic? Did it boot trusted firmware? Can I trust the keys inside it? Can I trust the communication between components? Can I prove that trust to the rest of the system? This is why the root of trust increasingly has to move closer to individual silicons itself. This is where architectures such as Caliptra become very important.
Caliptra gives us an open-source security architecture for establishing a hardware root of trust in modern devices. There is an important distinction here between a digital root of trust architecture and the physical security foundation underneath it. On the left, we have the Caliptra subsystem. Within the subsystem, the Caliptra core includes things such as the RISC-V processor, cryptographic functions, SRAM and ROM, mailbox and the firmware responsible for implementing the security architecture. Ultimately, all that digital security logic has to anchor itself to something physical in silicon. As you see on the right, there are three fundamental requirements for this physical hardware anchor, which we also call foundational security primitives. First, a unique device secret, UDS. We need something unique to the individual piece of silicon that can establish device identity and support key derivation. Second is a secure non-volatile storage.
Security-critical information such as life cycle state, configuration, seeds, or other protected value needs to survive power cycles and remain protected from unauthorized modifications. Third, a trustworthy entropy. All of the cryptography above this layer ultimately depends on good randomness. If the entropy is weak or predictable, the keys derived from it can also become weak or predictable. Caliptra provides the architecture and framework for the root of trust, but the foundation of that trust still has to terminate in physical properties and protected state inside the silicon. That is the physical security anchor, and those requirements actually match very naturally to technologies of hardware security that eMemory and PUFsecurity have already been developing for many years. This is where we move from the architecture to the actual silicon implementation. For the UDS, unique device secret, we use NeoPUF.
Rather than simply programming the root secret into conventional memory, NeoPUF derives device-unique information from the intrinsic physical characteristic of each individual piece of silicon. That gives us a silicon-bound foundation for device identity and key derivation. For secure non-volatile storage, we have NeoFuse, our OTP. NeoFuse provides protected storage for security-critical information such as life cycle values, seeds, configuration, or other persistent security assets. For entropy, we provide the physical noise source supporting the TRNG, true random number generator, giving the cryptographic system the randomness required for secure key generation and operation. On top of that, we're extending this foundation to the post-quantum era through PUF-PQC. Importantly, we view these IPs as different pieces of the same security foundation, identity, protected storage, trusted entropy, and cryptographic agility. Together, these are the types of silicon-level primitives that a framework such as Caliptra ultimately needs in order to establish trust.
But having the primitives is only part of the problem. For our customers, the next question is how to integrate all these pieces into a complete validated security system. This is where our strategy goes beyond selling individual IPs. We start with PUFrt as the hardware anchor IP. Around that, we add post-quantum security capabilities. Importantly, we have experience in integrating with Caliptra, because from a chip designer's perspective, the difficult question isn't just, can I license a PUF? The real question is, how do I turn the specification into silicon that actually works? How do I connect the hardware primitives to the Caliptra root of trust architecture? How do I validate the interfaces? How do I shorten integration and verification time? That is why we're moving towards a validated subsystem approach.
Once that foundation is available, the same security architecture can scale across accelerator boards, AI servers, rack scale systems, and eventually data center infrastructure. What starts as a very small security block in silicon can ultimately become the trust foundation for a much larger computing platform. That brings us back to where we started, this increasingly composed AI system. So the trust must extend across every layer of the AI infrastructure. AI infrastructure is becoming distributed across multiple layers. At the system level, CXL can protect data moving across a link through mechanisms for confidentiality, integrity and replay protection. But protecting the link does not automatically mean that the device on the other end should be trusted. That end still needs an integrity trusted firmware secure boot and also needs to be able to prove its state through attestation. The multi-die package follows similar principles.
Each active chiplet may have its own identity, keys, firmware, life cycle state, and relationships with the other dies in the package. So trust increasingly has to extend from the data center to the rack, to the server, to the device, to the package, ultimately down to the individual silicon, and that's why our foundational IP is so important. NeoPUF, NeoFuse, and our entropy source and PUF-PQC may be physically small pieces of an overall AI system, but they provide some of its most fundamental security properties, a unique identity, protected state, trustworthy entropy, and cryptographic trust. PUFrt bring those capabilities together as a physical hardware anchor, while Caliptra provides the architecture that builds a root of trust on top of them.
As AI compute becomes more composable and more distributed, we believe security has to follow exactly the same direction. Trust must also become distributed, but it must remain anchored in silicon. That is the role we see for eMemory and PUFsecurity's foundational IP, providing the silicon trust foundation that enables secure chiplets, secure CXL connected device, and ultimately the next generation of AI infrastructure. Thank you for your time.
This concludes our prepared statement. Next, we will enter the Q&A section. We will now begin the Q&A section. Please submit your questions in the input box on the webcast window. All of our questions will follow the format of answering the Chinese version first, followed by the English version. We will now collect the questions and begin our Q&A section.
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Our first question is in the previous earnings call, the company mentioned that royalty revenue was expected to grow in the second half of this year. Are you now confident in that outlook? Joseph, please.
Yes, our outlook remains the same. We have already seen several advanced node products, including ADAS, AI accelerators, SSDs, networking, and other new products. They begin to enter the mass production phase. In addition, with foundry wafer prices gradually increasing, we believe the growth momentum will continue to accelerate. Thank you.
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The company has mentioned that the number of customers using 3 nanometer technology have already been licensed or taped out. Could some of them be contributing to royalty revenue in the second half of this year? Joseph, please.
Yes, we have already seen customers moving into mass production with several hundred wafers, and this indicates that their products have been successfully validated. The contribution expected to become much more meaningful next year.
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AI data centers are driving upgrades in high voltage power architecture such as 400 V and 800 V HVDC as well as next generation power ICs. Has the company started to benefit from this trend? Which product lines will be the main beneficiaries? Joseph, please.
Yes. For eMemory, the upgrade of AI data center power architectures creates opportunities through our IP being integrated into power management, power control, and related analog mixed signal chips. As voltage levels and power density continue to increase. For power ICs, they require much more precise calibration, parameter compensation, device identification, and also reliability management, and of course the security functions. The related IPs we can provide mainly includes OTP, which is mainly being used for analog parameter calibration, trimming, power control setting, and of course, product identification. For MTP, they can support system parameters and configuration setting that need to be updated multiple times. Our customers have already started to move into mass production, and we expect the contribution to expand further in the coming quarters. Thank you.
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Could you share how investors should think about the contribution from advanced node product to your royalty revenue today and how you expect that mix to evolve over the next few years? Joseph, please.
In terms of licensing NRE contribution, advanced node projects already accounted for more than 50%. This is mainly because the licensing fee for a single advanced node project is several times higher than average project licensing price. Looking ahead, as these projects gradually move into mass production, we expect royalty contribution to increase meaningfully as well.
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Royalty revenue declined in the second quarter compared with the first quarter. Could you please help explain the main reasons behind the decrease? Joseph, please.
For our Q2 royalty revenue, they correspond to the foundry production in the first quarter. Overall, mature foundry capacity utilization remained at a relatively low level in Q1. Some customers were also going through seasonal inventory adjustment. Starting from the second quarter, overall foundry capacity utilization began to improve, while new applications started to enter mass production. Together with subsequent impact from foundry price increases, we believe royalty revenue is expected to accelerate in the second half of 2026. Thank you.
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As 2 nanometer and GAA processes gradually move toward mass production, have the competitive advantage of NeoPUF and NeoFuse in advanced nodes become even stronger? Are customers also adopting this technology faster than they did last year? Charles, please.
As the process technologies move from 2 nanometer and GAA, chip design and the manufacturing costs continue to rise, and the customers are placing even stricter requirement on area, power consumption, reliability, and compliance with security standards. In this environment, the competitive advantage of NeoFuse and the NeoPUF-based security IP become even more apparent. NeoPUF can create an unique hardware identity at the silicon level for each chip, supporting key generation and hardware root of trust. NeoFuse provides reliable OTP storage, and for the chip configuration, code patching, SRAM repair, and other functions. This capability can be integrated with advanced logic processes and support the security, reliability and the higher requirement of advanced SOC. Compared with the past, we are indeed seeing customers start discussion on the security architectures earlier, and the number of application under evaluation is also increasing.
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As more PUF license enter mass production, how do you expect the mix between licensing and royalty revenue to evolve? Charles, please.
Based on our operating performance in recent year, our PUF business has delivered very strong growth in both licensing and royalty revenue. We believe this trend is still in the early stage because due to the AI booming very fast, and now there are a lot of demands to secure the AI's applications. So we believe that the license fee and also royalty, due to the application of PUF, will be increased.
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Could you share the latest progress with customers for 1T Flash? Is there a possibility that it could start moving into mass production within the next year or so? Charles, please.
For 1T Flash, we are currently working with several foundries partners on platform development and verification. Each platform is progressing according to its development plan. We may see customers begin mass production next year.
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Your security IP has expanded from AI CPUs and BMCs into AI data center SSDs and CXL related applications. Does this suggest that eMemory's security IP is moving from a single chip to multiple critical chips within an AI server? Where do you see the next major opportunities? Felix, please.
Yes. As AI server architectures continue to evolve, we are seeing hardware security requirements extend across different parts of the system. These include computing, storage, connectivity, and system management. This gives our security IP opportunities to address a much broader range of chips. Our licensing activity in the first half also reflects this trend with applications across CPUs, storage devices, optical communication ICs, FPGAs and high-speed interface chips. For us, the opportunity is not simply about adding more customers. It is about expanding our security footprint across AI infrastructure, while also providing more security functionality within each chip. As a hardware root of trust, data protection and system-level security become very important for the AI infrastructure. We believe that there is significant room for our security IP business to continue to grow across AI and data center applications.
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Will NeoFlash compete with NAND Flash used in enterprise and consumer SSDs such as SLC, TLC, or QLC? Or does it address a different market? Charles, please.
For standalone application, our initial development focus is mainly on the NOR Flash. The NOR Flash and the NAND Flash are two different memory technologies with different positioning. They mainly address different application needs. NOR Flash is focused on fast boot, low latency, random read, and execution in place, or XIP, and high reliabilities. Therefore, it is mainly used to store firmware and system call. NAND Flash, on the other hand, is mainly designed for high capacity and low cost, making it more suitable for the large-scale data storage applications. However, after foundry partner successfully move for standalone NOR Flash into mass production, we may further extend 1T Flash into NAND Flash architecture in the future.
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As cybersecurity regulations such as the EU Cyber Resilience Act, or CRA, gradually come into force at September this year, how does the company view the adoption trend of PUF in advanced-node SoCs? Felix, please.
With the CRA expected to become mandatory, non-compliance may result in significant penalties. The regulation also applies broadly to all connected products sold in the European market. As a result, the market is placing great emphasis on cybersecurity compliance. At the same time, the concepts of Secure by Design and Secure by Default are increasingly becoming industry consensus. In such a context, PUF, as a key technology for hardware root of trust, plays an important role in device identity and key protection. As regulatory requirements become more stringent, we expect demand for related security mechanisms to continue to increase.
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Has eMemory's IP been adopted in application related to low Earth orbit or LEO satellites and space communications? Joseph, please.
Yes, our technology has already been adopted by U.S. customers for Low Earth Orbit satellite applications. Given that satellites, they operate in extreme environments and are non-recoverable once launched, our OTP provides four critical safeguards. First of all is radiation hardening and high reliability. Because in space, intense radiation can cause bit flips in traditional flash or EEPROM solutions, and they can lead to data errors and mission failure. Our OTP, on the other hand, they store data by permanently altering the physical circuit structure, so once written, they remain immune to radiation, making it the most secure place to store critical boot code. Second is for secure communication and key storage. As satellites, they function as massive network nodes. Cybersecurity is critical, and our OTP stores encryption keys and digital certificates that cannot be remotely tampered with or erased.
This establishes a robust hardware root of trust, protecting the communication between satellites and also the ground stations from hacking attempts. Third is hardware identification. For a constellation with thousands of satellites, precise management is vital, and each chip should be programmed with a unique ID during production, which is essential for fleet management, fault tracking, and automated spectrum licensing verification. Lastly is a parameter compensation for extreme environments. As you know, to withstand drastic temperature fluctuation in space, our OTP stores calibration and compensation parameters for precision sensors, and this ensures that electronic signals, they can remain accurate regardless of the extreme thermal conditions. Thank you.
In the interest of time, we will begin the last questions.
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Being removed from the MSCI index, coupled with our relatively high foreign ownership, may raise concerns about potential heavy foreign sell-off and how the company plans to respond.
MSCI index inclusion is primarily based on market capitalization ranking, and is not the reflection of company fundamental. In fact, 10 years ago, when we are not including in the MSCI standard index, our foreign ownership of our shares already above 50%. At the end of July this year, our foreign shareholder actually is a record high, like 67%-68%, just slightly lower than the shareholding of the TSMC foreign shareholding. We have reached out to our major foreign shareholder, and their response that the index adjustment will not affect their investment decision. As for passive fund rebalance, experience show that the index constitute change are largely predictable during quantitative model, so the market usually discount and absorb the impact in advance. The foreign selling pressure observed since early August likely reflect this passive fund adjustment.
To mitigate significant stock price volatility, we will proactively enhance our communication with the capital market, especially local institution investor. We plan to participate in more investor conference and expand analyst research coverage, proving the company true value through our strong fundamental and operating result.
Next, we will begin the closing comments. Charles, please proceed.
Thank you for attending our investor conference. For more information about our PUF-based security IP and technology, we encourage you to visit our PUFsecurity website and check out our articles and other materials. Thank you once again for your patience and the support for eMemory. We will continue to work hard on technology and IP innovation, and PUF-based hardware security solutions for our customers, and bringing higher returns for our shareholders. Thank you.
Thank you, ladies and gentlemen. Please be advised that the conference recording will be accessible within the next three hours. Thank you everyone for joining us today. We hope you will join us again next quarter. You may now disconnect. Goodbye and have a good day.