Thank you for participating in Advantest's IR Technical Briefing today. I will be your moderator. I'm Kobayashi from Corporate Planning, Strategy Group. Products that we provide are deeply interrelated with not only semiconductor volume, production volume, but also has to do with technology evolution of semiconductors. To provide such interrelation, we host such technical briefings regularly. Today's focus will be tester demand for memory, semiconductor market, as well as solutions we provide. I will introduce you the speakers. So Masayuki Suzuki, Executive Vice President, Memory Test Business Unit, ATE Business Group. Mr. Jin Yokoyama, Department Manager, Memory Test Business Unit, ATE Business Group. Today, Suzuki will first explain memory testers business environment, followed by Yokoyama's presentation on memory semiconductors, test needs and solutions. After that, we'll take questions from you. We plan to end the session at 5:00 P.M.
Today's session will be distributed in simultaneous translation in Japanese and English. If you prefer to listen in Japanese, please click on the globe icon on the lower left-hand side of Webex screen and choose a menu that says Interpretation Language to choose Japanese. Underneath, there's a menu that says Balance. Please select the bar and slide it all the way to the right-hand side to Interpreter, so that you can listen to Japanese during our English presentation. If you prefer to listen the original audio in Japanese and English, you don't need to change the setting. You can use the default setting. Today's presentation material is available on our homepage. The presentation we will be projecting will be in Japanese. If you prefer to follow the English presentation or if you're dialing in through a telephone line, please download the respective presentation material.
Before we start the session, we have a disclaimer. The explanations we'll be making will include forecasts, as of today. However, these forecasts, involve risks and uncertainty. Please note that there might be discrepancy between the actual result and the forecast. Now, we'll pass the mic to Suzuki-san.
I'm Suzuki from Advantest. Good to speak with you today. Today, I will explain about memory testers business environment. Semiconductors support safety, security, and comfort in our daily lives. The applications of semiconductors are expanding, and technological advancements are making our lives more convenient and comfortable. In memory semiconductors as well, more and more memory semiconductors are being used as the range of applications expands. In addition, memory semiconductors are undergoing an increase in density and performance, given continuous advancement in end products, continues to increase.
This slide shows a memory major applications that will drive the next generation of memory market. In particular, memory semiconductors used in smartphones and servers in data centers are driving the memory market with higher functionality and increased density. These are displayed on the left-hand side of the slide. In addition to the evolution of performance in smartphones, such as higher definition and multi-lens cameras, recently, functions such as AI and large-scale language models are being deployed. The emergence of new technologies such as generative AI is also expected to drive further capacity expansion of data centers and in the server-related sector. Accordingly, memory semiconductors are expected to see higher performance and increased density, as well as an expansion in supply. In high-performance memory, DRAM for high-performance computing, HPC and AI are expected to be the main drivers of the memory market, along with smartphones.
The graph on the left-hand side of the slide shows sales of DRAM and NAND flash in the overall memory market. Since 2017, the baseline of memory semiconductor market size has increased compared to the past, supported by expanded smartphone functionality and growing demand for data centers. Under those circumstances, we saw an increase in demand for 3D NAND flash products, as well as a rise in added value and supply of memory products, alongside technological advancements, such as the transition to the DRAM such as to the DDR4 generation. This year, in 2023, market conditions are deteriorating due to continued inventory adjustments by memory semiconductor manufacturers and falling investments in consumer and data center applications. However, the overall market is expected to expand rapidly going forward due to expectations for a rapid increase in demand for high-performance memory, inspired by factors such as Generative AI.
The market forecasts for HBM is for a five-year CAGR is approximately 52% over the next five years, from a period of 2023 to 2027, which is higher than the average growth rate of around 21% for DRAM as a whole over the same period. We would now like to explain how the memory tester market has been trending in the memory semiconductor market. The memory tester market is affected by fluctuations in memory semiconductor production volume. However, more than production volume, factors such as increasing density, faster interfaces, and higher reliability assurance are the main drivers for growth in tester demand of memory semiconductors. During the previous down cycle in 2019, the memory tester market shrunk by more than 40% from the previous year due to deteriorating memory semiconductor market conditions and inventory adjustments.
Turning to 2020, the shift to DDR5 generation in LPDDR for smartphones began, leading to an increase in tester demand. An increase in memory density led to an increase in demand for tester volume, while faster interface speeds led to replacement demand for next generation testers. In the most recent down cycle of 2023, the size of the tester market has been affected by memory market. However, compared to the previous decline, we expect the trough to be shallower, as there will be some offsets from a certain amount of increased tester demand for high-performance memories such as HBM and DDR5. Going forward, in addition to the recovery of the memory market, we expect the market size to expand in 2024 due to the strengthening of testing to ensure high reliability in high-performance memory. This is already stimulating tester demand in the near term.
We feel that memory tester market is transforming into a less cyclical growth market compared to the past, although it is still subject to fluctuation in the semiconductor production volume. Next, I will explain our position in the current memory tester market. We have three major core competencies. The first is our advanced technological capabilities and leadership in the memory test industry. Since the 1990s, we have continued to provide close technical support to customers developing leading-edge technologies for more than 30 years. We have accumulated a wealth of experience and solid technical capabilities in memory testing by closely following the technological evolution of memory semiconductors. For the year 2022, we have maintained our leading-edge position in memory testers with an estimated 53% market share.
By being the first in the industry to launch optimal test solutions, especially for high-end memory, we have consistently established a de facto standard position in memory testers. Second, we have the industry's number one product portfolio and comprehensive solution capabilities. In addition to the product portfolio that covers the entire memory test processes, which we will touch upon in the next slide, we are also able to offer comprehensive testing solutions, including peripheral equipment, which gives us a competitive advantage. Our industry-leading product quality with low failure rates helps our customers maximize their volume production efficiency. Third, we have established the industry's largest and most solid quality customer base.
Our expert engineers, who embody the advanced memory test knowledge and experience we have cultivated over the years, are positioned globally to provide timely technical support for everything from memory semiconductor development to volume production, earning us the trust of a wide range of customers. This slide shows one of our core competencies introduced on the previous page, a product portfolio that covers all memory testers, memory test processes. By proposing a combination of our technology-driven product lineup, from device interfaces to test handlers, which are test-related peripherals, we are able to provide our customers with comprehensive support for setting up test environments. This is a factor which differentiates us from our competitors. Lastly, I will provide an explanation, an example of how we can help customers set up a comprehensive test environment.
The product on this slide is called Intexcel, which is an industry-leading test solution that integrates memory test, device interface, and auto handler technology. This is an industry-leading integrated solution that responds to the technical evolution and an increasing supply of memory semiconductors, for which demand is expected to grow over the medium to long term. It is a state-of-the-art solution that addresses the challenges associated with packaging testing of memory devices, such as higher performance, lower power consumption, and faster interfaces. Operationally, the most important feature of Intexcel is its scalability in system configuration and its ability to minimize footprint. The solution contributes to higher utilization rates by supporting control of each small test cell individually in the volume production process and facility automation, while at the same time reducing footprint to about one-third of that of our conventional products.
We were able to design a very compact chamber structure for setting the temperature environment during testing. Improved thermal efficiency helps to reduce power consumption required to set a wide range of temperature environment, ranging from high to low. This new solution will support our customers' technological evolution, while at the same time helping to improve production efficiency and energy efficiency at testing. This concludes my presentation.
Hello, I am Yokoyama. Sorry. My presentation, titled Memory Semiconductor Testing Needs and Solutions, will focus on HBM, a type of graphic DRAM that has received the most attention in the memory industry recently. First, I will provide an overview of memory semiconductor test flows and explain memory test characteristics, as well as the main drivers of tester demand. Please see the upper right corner of this slide. This slide shows a simplified test flow for a typical DRAM and NAND device. Both DRAM and NAND go through a burn-in test process under high temperature and high voltage to eliminate initial defects, and then a test process to confirm that semiconductor functions as designed by applying electricity. There are many test processes. Conditions such as temperature settings are added to the test process, and devices undergo tests many times.
As shown in the lower right-hand corner of this slide, there are test needs and technical challenges for each of its processes in memory semiconductor testing. In general, testing conditions become more demanding as the semiconductor undergoes a number of steps from the wafer test to the final package test. In DRAM, for example, memory interface speeds continue to increase with generational changes such as DDR4 to DDR5. Accordingly, post-packaging testing is divided into burn-in and core test at actual operating speeds, and interface speed test to test DRAM at high speed. Demand for memory semiconductor testers arises primarily from three factors. The first is bit growth, which is a multiplication of the number of chips shipped and density. Bit growth results in longer test time and drives tester demand throughout the test flow. The second is the increase in memory data transmission speed.
This causes demand creation for high-speed testers with new test coverage. The third is the increase in production volume of high performance memory semiconductors for AI or HPC and other applications, and the requirement for higher reliability. I will explain this in detail in the following pages. Please turn to page 13. This slide shows technology trends and future prospects for DRAM interfaces, including high-performance memory, which is expected to drive the memory semiconductor market. In this chart, the composition of each DRAM device is based on bit conversion. Bars from 2017 to 2022 are based on actual results, and bars from 2023 to 2027 are based on forecasts. From 2023 to 2024, the generation shift to DDR5, mainly for PCs and servers, will continue, and DRAM speeds and density will continue to increase.
In addition, LPDDR, a low power consumption device mainly used in mobile and automotive applications, is also expected to see higher speeds and density, and demand for LPDDR5 and 5X is also increasing in data centers. The transition to the DDR5 generation will create demand for higher speed interface testing and will also lead to increased demand for tester volume due to bit growth. HBM, which is at the top of this chart, also continues to increase in speed and density.
Against the backdrop of higher quality requirements from end products, elaborate testing is being carried out to increase the percentage of good devices, and there has been a steep rise in tester demand as we speak, including longer test time and additional test processes. Although the percentage of HBM in the total DRAM market is expected to be around 10%, we expect to see a rise in demand for testers driven by higher density, faster interface speeds, and higher reliability assurance. Please take a look at page 14. Let me briefly explain about HBM, which is now expected to grow at the highest rate. Since the end of last year, the rapid expansion of generative AI and advanced LLM has accelerated the demand for high performance AI modules in semiconductors such as GPUs and HBMs.
As shown on the right-hand side of the slide, HBM uses 3D stack memory technology to provide higher bandwidth and density scalability, and side-by-side connection on the same substrate with the latest associated accelerators, such as GPU and custom ASICs, provides higher processing power, thereby supporting higher performance of the entire system. Although today's HBM is set to face challenges for the next stage of further scaling due to manufacturing costs and thermal control issues, further performance improvements are being deliberated as the learning curve picks up for the next generation stacking technology. These GPUs with high parallel processing capability with thousands of cores or more and HBM with this optimal configuration are essential for future AI technology, and therefore, the market is expected to grow at a high rate. Next page, please. Page fifteen.
We will now explain HBM technology trends and future prospects. The graph on the left-hand side of this slide shows shipment of HBM on a bit basis. Over a five-year period from 2023 to 2028, growth rate of about 50% is expected. The table on the right-hand side of the slide is a comparison of HBM performance improvements expected from generation transition. Our marketing department compiled trajectories from HBM2E to HBM4 based on the evolution by memory bandwidth, density per die, stack count, and speed. The current mainstay in HBM2, 2E has density of eight gigabit or 16 gigabit per die and has eight, four or eight stacks. Speed is estimated to be 3.2 Gbps or higher.
As we move into the next generation of HBM3, its enhanced versions and HBM4, we expect to see a one point five times to nearly two times increase in density per die and stack count, as well as a nearly doubling of speed and total memory bandwidth. Such scaling and scalability is directly related to increased testing demand. Next page, please. Page sixteen. The following is a simplified image of how memory manufacturers are currently testing HBM and the challenges they face in testing. The figure on the left shows an image of the testing process from the time the DRAM wafers that make up the HBM and the logic wafers that serve as the interface are manufactured to the time the HBM is shipped. The light blue DRAM wafers shown at the top are likely to undergo a testing process similar to that of conventional DRAM memory.
The orange logic wafer in the middle will also undergo a simple wafer test. The HBM wafer is then completed via the 3D stacking process at the intersection of the light blue and orange arrows. The process then shifts to the post HBM stack process in blue at the bottom. Multiple insertions are likely to take place, such as memory cell access and functional tests. Quality will be improved by undergoing those multiple test insertions, and they'll be shipped finally. Going forward, as the HBM market expands and memory performance improves, various test challenges are expected, including memory density increase driven by an increase in stack count, rising interface speed, and impact on parallelism from an increase in device power supply, as well as electric current. In order to handle such challenges, testers need to harness greater scalability.
In addition, in response to yield impacts on dicing of HBM wafers, countermeasures such as introduction of die-level testing post-dicing is being discussed. Currently, we have a high share of the HBM market. We will continue to research and develop the best solutions for future needs in a timely manner by anticipating all possibilities and by taking advantage of our broad product portfolio. Next page, please. Page seventeen. Social implementation of Gen AI has just begun. Driven by demand related to Gen AI, high-performance memories such as HBM and DDR5 are expected to enjoy high market growth. As packaging capacity for advanced packages such as 2.5D and 3D increases, production volume of such high-performance memory is expected to grow. In addition, test parameters and test processes are being enhanced in terms of further quality assurance of semiconductors as they become more performant and gain complexity.
As a result, we see further opportunities for our memory testers business, which we believe will be the key to our future growth. Finally, the last page. We will summarize the business environment for memory testers and the expansion of test demand. As explained at the beginning, memory semiconductors are continuing to increase in performance and density in all domains. Among these, in particular, we expect the technological evolution and market growth of HBM and DDR5, which are high-performance memories, to drive the market going forward. We will continue to lead the industry and contribute to the realization of safety, security, and comfort in society by firmly supporting the technological evolution and growing demand for memory semiconductors with our continuously evolving advanced technological capabilities for our portfolio and solid quality customer base. This concludes my presentation.