Ladies and gentlemen, thank you for standing by. I'm Mandy Schmeckebecher, your operator today. Welcome, and thank you for joining the AT&S Conference Call on Results for the First Quarters, 2025, 2026. Throughout today's recorded presentation, all participants will be in a listen-only mode. The presentation will be followed by a question and answer session. If you would like to ask a question, you may press nine and star on the telephone. If any participant has difficulty hearing the conference, please press zero and hashtag for the operator assistant. I would now like to turn the conference over to Mr. Philipp Gebhardt.
Thank you, Mandy. Good morning or afternoon, ladies and gentlemen. Welcome to the AT&S nine months 2025, 2026 conference call. I'm delighted to welcome our new CFO, Gerrit Steen, to his first quarterly call for AT&S. As he has just officially joined us yesterday, our VP of Finance, Silvo Leitner, as in the previous call, will present the figures and answer any financial questions. However, in the recent months, we have received an increasing number of questions about current technical developments. We see that as a positive sign that the focus is shifting from our balance sheet back to our core business. Therefore, we would like to use this call to answer these technical questions in a more qualified manner than if they were addressed to me. I'm therefore particularly pleased to welcome our CTO, Peter Griehsnig, today.
He will address the two current trends directly in the presentation, and will also be available to answer your questions afterwards. So after this introduction, please allow me to begin on page two. As planned, Kulim and Hinterberg are now contributing to revenue. This marks an important milestone in our capacity expansion and supports our top line growth, bringing us up to EUR 1.3 billion in revenue. We also see positive momentum on profitability, product mix improvements, and a more favorable pricing environment in Q3 have supported the margin recovery. In addition, our efficiency programs continue to contribute to earnings and make a significant impact on our EBIT of EUR 35 million. On the downside, currency fluctuations, in particular, the weak US dollar, created notable FX headwinds, partially offsetting both top line and operational improvements.
Nevertheless, supported by the restart of our factoring program, we achieve a positive operating free cash flow of EUR 223 million, demonstrating the strong cash discipline. While global dynamics remain uncertain, we are seeing sentiment in our core markets becoming more positive. Based on the current performance and the outlook ahead, we have confirmed our full-year guidance, as well as the guidance 2026, 2027. Moving on to slide number three. The PCB market grew by 15%, 15% year-over-year, or 11% in euro terms from 2024 to 2025. This growth is driven primarily by increased demand in high-end computing, networking, and advanced packaging applications. The IC substrate market also expanded last year, growing 18% or 40% in euro. This continues to be supported by strong AI-related investments and ongoing data center build-out, which remain the growth engines.
I'm continuing on page number four. After adjusting the number of our supervisory board members last year, we now have, as of February the first, also reorganized the management board. Instead of five members, the company will be led now by three: Our CEO, Michael Mertin, our CTO, Peter Griehsnig, and our CFO, Gerrit Steen, to whom I would like now to give the floor.
Thank you, Philipp, and good morning, good afternoon, good evening, wherever you are, everybody. My name is Gerrit Steen, and I'm very happy and proud to have joined AT&S as CFO, actually yesterday. So my immediate focus now is on gaining a detailed understanding of the business, the markets, and the financial position of the company. But I can tell you already now that I have had very positive first impressions of the commitment and dedication I have seen across the organization. But for today, as Philipp already alluded to, I will primarily listen and leave the explanations about our last quarter in the very capable hands of my new colleagues. Certainly happy to support the discussion later, where relevant. So thank you, and over to you, Silvo, to guide us through the numbers.
Okay. Also, welcome from my side. I will lead you through the figures, starting with the consolidated group. You can see very nice on, on a year-to-date basis, we increase in our revenues from EUR 1.1 billion to EUR 1.3 billion, so roughly +10%, and also a very nice development from quarter to quarter, roughly plus eighteen percentage. We are landing now in the third quarter with a revenue of EUR 468, coming from positive product mix, volume, and pricing impacts, but also from the ramping. On the next slide, we go to the BU Electronic Solution. There you can see if we take Ansan out and compare apple to apple, I will say, we can see a year-to-date revenue somewhere flat with EUR 670 million, so zero increase.
Over quarter-to-quarter, you see a declining of 4%. But you have to take into account that here we have the seasonality of the mobile devices business, and even in the last Q2 quarter, we have really a nice revenue of EUR 256 million, so a little bit also on timing differences. Maybe next slide. Here we can see the business unit, Microelectronics, with a very, very nice development here to date. We see we are growing from EUR 463 million to EUR 621 million, sure, coming from the ramp in Kulim and Leoben, supporting also with volume mix and price increases and developments.
Also, quarter over quarter, you can see a 65% increase from 154 to 254, and even quarter to quarter, Q2 to Q3, nice increase and also an increase in the margin. And I think that is for microelectronics. Coming to the maturity profile and our financial position. Also, here you see a very nice solid financial structure. We have EUR 886 million cash and cash equivalent, most of it, 843 in a cash and cash equivalent, and some unused credit lines is 43 million. If you look in our profile on the left side, you can see for this year, we have roughly EUR 140 million to repay next year, 488.
That is easily handled with our EUR 808 million in our pocket, I will say. Also, the financing costs are very nice, with 3%. Everything from my point, very well. On next slide, you see our working capital that we always show. I think we have a healthy level now with 14.6% or 13.6% in our Q3. You know, before this 19%-18%, what you see in the quarters before is coming from our factorings that we leveled out over the time. On next slide, the cash flow. Cash flow from operating activities, also very strong, I was coming from EBITDA and also a little bit helping from the factoring, EUR 332 million.
Also, the cash flow from investing activities, very nice, driven by the cash deposits that we have in the last year, but also lower CapEx, -26, financing, 83. Also, okay, so we come to an operating free cash flow of EUR 223 million in this year. Last year, we had a minus of EUR 357 million. So, and the net CapEx is 812 is EUR 108 million. So everything, I think, also very well. Balance sheet, total assets, flat, EUR 4.6 million. Equity, we lose a little bit out of the headwind of the X, mainly in the U.S. dollar.
Equity ratio is with 20.8%, and also in the net debt, we can reduce it from EUR 1.4 billion to EUR 1.3 billion, and the net debt EBITDA ratio is 2, is also very nice, I will say. On next slide, the cost-saving program that we always show. Our target, as you know, is EUR 130 million. We achieved this in the third quarter, and our expectation is that we land at the year-end at EUR 160 million+. Next slide, I can confirm, as you have here, also in the beginning, the guidance for 2025, 2026, we will stay with the EUR 1.7 billion. The margin is, as mentioned, also in the last quarter, 23%.
The net CapEx will reduce from EUR 250 million to EUR 200 million, and we will stay with a positive EBIT and operating free cash flow. Also the guidance for the year 2026, 2027 will stay, as also mentioned in the last quarter, between EUR 2.1 billion and EUR 2.4 billion. As I mentioned last time, have in mind that we have had wind from the FX and also a little bit maybe on, on glass shortage, S-glass shortage. So, we see us at a lower level, and other things are unchanged. I think that's from my side.
Over to you, Peter.
Right. Good afternoon. Good evening to everyone. This is Peter G riehsnig, CTO of AT&S. Allow me to take a few minutes to shine a little light on technology trends in the area of substrates, in particular, substrates for artificial intelligence, because that's where the action currently is. AI has definitely changed the speed of progress, and with the traditional transistor scaling not being able to deliver what is needed, what is needed as fast as it is needed, the industry turned to the package to support, and with the package, also the substrate. So what are actually the challenges of the industry, where substrates can support, where substrates need to innovate to deliver their input? It's basically what's mostly three topics.
One is the size of packages, the other one is the data rates, and the third one is the power delivery for those processes. Now, why are these challenges and what can we do as substrate manufacturers? In order to understand that better, we need to look at the architecture of such a processor package, and you see that in three different variants... Take the middle one first, CoWoS. CoWoS is the workhorse of the industry. This is what TSMC does. This is how almost all the current AI processors are built up. It consists first on top of the active dice, the memory stack, and the GPU, which is connected first by a silicon interposer. Then all the signals that go in and out of the package are routed and fan out by the substrate.
The substrate also routes the power to every place in that package where it's needed. And these three top layers is what generally is called the package, and the package is then connected to a much larger PCB. That architecture works quite well so far, but it comes with its own challenges. When you want to increase the processing power, what you can do and what you must do is put more GPUs and more HBM, the high bandwidth memories, into that package, and that increases the size of the package significantly. Over the last couple of years, package sizes have quadrupled, and going forward, they will quadruple again. Very soon, you will see substrates the size of a tablet. That means, of course, massive more manufacturing demand. Not only the unit numbers increase, also the unit size increase will increase dramatically.
Of course, also technology-wise, this is extremely challenging to deliver the very, very tight specifications that are necessary for a substrate on such large package form factors. What we can do, what we need to do, is use alternative, new, more exotic materials. They will be, of course, more expensive. They will be thicker in order to keep warpage under control. And ultimately, this may or may not lead to the introduction of glass-based substrates. What also is a challenge coming from the package size is how to scale up the silicon interposer on top of our substrate. That's a large piece of rectangular silicon cut out from a circular wafer. That's not good when you want to scale it up. There are natural limits to do so, and it is becoming hugely expensive.
So, what to do going forward? Multiple options are there. First of all, it would be an option if instead of cutting it from a round wafer, if we would cut the interposer out of a panel, similar to what we do, a rectangular format, the size of maybe 0.5 m by 0.5 m, you could fit in many more. You would have much less waste, but it probably won't be silicon anymore. It should preferably be something organic, which then comes close to what we in substrates do. Of course, the challenge will be to achieve those fine feature sizes that the semiconductor industry can do with silicon. 1 micrometer or below 1 micrometer line space is something that is very, very difficult to achieve with organic material as of now.
But if we look further into the future on the longer horizon, it is an option, what could be done. There is already today something that is a smart solution to scale up the size of packages, and that is when you look to the left side, it's called EMIB, Intel's basically Intel solution. And the thought is simple: You don't need an interposer full size. All you need is a connection from one edge of one die to the other edge of the other die. And so you can break down the interposer in multiple small pieces, which are called bridge dies. And when you scale up the size of the package, you need more of them, but not a bigger one.
That makes scaling way more economic, and the larger the package size will be in the future, the more benefit this kind of architecture seem to have. So going forward, if Intel can get some design wins in the market with that kind of technology, their share in the market could probably increase based on the smartness of that of that package architecture. And currently, and probably also going forward, there is less than a handful of suppliers that can manage and manufacture the extreme tight tolerances that are necessary to embed those silicon bridges slightly under the surface of the package substrate. So that solution has taken the advantage of merging interposer with the substrate effectively eliminating the interposer, at least for some applications.
There's also another opportunity that you see on the right-hand side, where the substrate is merged with the printed circuit board, effectively eliminating the substrate. That's what's called CoWoP. It is a new technology promoted by TSMC, and NVIDIA is trying to build such kinds of packages in the near future. However, the challenges are substantial. The challenges are, the PCB already is not so easy to make. It's a high layer count board and a large board. Now you need to merge it with the additive processing technologies of a substrate, and you need to fulfill all the tight specifications that usually only were applicable to smaller, much smaller substrates. Can that be done? Technically, probably. Economically, question mark.
The future will show us how well that kind of architecture can work. Why would any customer want to have that? What's the benefit out of it? There are lots of benefits. Probably the one that is reported quite often, the cost saving, I have serious doubts that this will be much cheaper. But what definitely can be a benefit is addressing the second difficulty, which is data rates. Signals in order to keep this GPU running, you need to bring into the package and out of the package, massive amount of data. A GPU makes easily 100 trillion operations per second, and accordingly, you need to bring in data constantly. It's not a secret that GPUs are idle significant time because not enough data are available. So solving that issue would be very, very beneficial.
And signals, first of all, don't like to travel long distances, and secondly, they don't like to go through different metal while they travel along a conductor. So when I take out the substrate, I cut out 18 layers of substrate. Signals definitely like that. And also one of the layers of microballs, which is a complex sequence of copper, nickel, palladium, gold, and tin. And signals also would like it if you take them out. Data rates could be increased by such a solution. Whether it's feasible to do so, we will see. Definitely as a substrate manufacturer, you want to be prepared, should this kind of architecture pick up in the future. Then, the third topic. If... Before we talk about power, let's have a look how these such a package looks like in reality.
You see the AMD MI350 accelerator, bottom left. In the middle of that picture, the colorful thing are the GPUs, surrounded by these squares, which are the memory stacks. They all sit on this darker gray, which is the silicon interposer, and then you see slightly greenish with a lot of yellow dots. That's our substrate. And that's basically the package, with a metal frame around it, and that sits on what's called the accelerator card, a large PCB that has, amongst other things, most of the power, the last stage power conversion on it. And that power conversion are all these black cubes that you see at the edge of the PCB.
That's the important topic that we need to talk about, because power delivery has come from being a sideshow to the main stage of designing powerful processors. Such a processor today needs easily 1 kilowatt, and that's current generation, and you can expect to double that in a few years and to quadruple even further down the road. That's massive amount of electrical energy that you need to feed into these processors through our substrate. And the art is to deliver that electrical power without losing half of it on the way to the processor. One noteworthy thing is that these processors run, unfortunately for us, at very, very low voltage levels, like 0.7 volt or 1 volt.
That means we need to route about 1000 amperes through the PCB first and then through the delicate structures of our substrate. That's not that easy. 1000 amperes is twice the amount of current that a Tesla Supercharger would use to charge the battery of your EV. A lot of losses are happening at such gigantic currents. We can help. We cannot reduce the power that the processor needs, but we can help to reduce the losses significantly. Now, these power modules here, indicated as PMIC power management IC, also called voltage regulators, they reduce the voltage level from the incoming, let's say, 12-volt to the 0.7 or 0.8 or whatever voltage the processor needs. While it converts the voltage, it loses power.
And the amount of power that gets lost is directly linked to the distance of the components inside this module. So the closer you can bring components, the less losses you will see, and it's perfect, a perfect application for our embedding technology. With embedding, we can bring components from millimeter distance to micrometer distance, and effectively cut down the losses that happen in all these black cubes that are there for power conversion. And in the next step, power loss also depends on the distance between this PMIC and the active dies. The longer the route is, the more power gets lost. So why not bring this power conversion stage closer to the active dies?
We can do that by, again, embedding it, for example, in the PCB, bringing it down from 5 cm to 1 cm distance, or we can even go one step further and bring the power conversion into the substrate, effectively reducing the distance to the die to millimeters. And again, embedding technology is the crucial part, the crucial enabler of reducing the losses significantly. We have shown for these PMICs that power loss can be cut down in half. A first generation of such product is already out in the market, very successful. We're working on next generations, and the demand is picking up significantly in the future.
With that, I hope I have given a little light on what's going on, what are the challenges, and what are the trends on the physical layer of artificial intelligence. With that, I believe we are open for questions.
Okay. Yeah. Thank you, gentlemen. We will now start the Q&A, and in order to give everyone the opportunity to raise questions, we would like to ask you to limit yourself to two questions. You know the game. Once we are through, if there are still questions and time, we will start another round. Now, I would like to hand over to Mandy to handle the session.
Thank you. Yes, ladies and gentlemen, it is time we begin the question and answer session. Anyone who wishes to ask a question may press nine and star on the touchtone telephone. If you wish to remove yourself from the questioning queue, then please press three and star. So please press now nine and star if you would like to ask a question. And I can see the first question from John Brown, from Citi. The floor is yours.
Yeah. Hi, guys. Thanks for taking my questions. I have two, if I may. I can take them one at a time. Just firstly, you know, we've had a stronger Q3 report this morning, but you've not changed the full year sales outlook. So I'm just looking at EUR 1.7 billion, you know, then that implies basically quite a big sequential step down in Q4. You know, however, we're, you know, we've seen news around pricing and ABF substrates improving from the beginning of this year and stronger demand for server applications from, you know, Intel, AMD, et cetera. Apple, of course, just had a great quarter and is sort of, you know, now in supply chase mode, as they sort of stated on their earnings call.
You know, I'm just wondering how we should interpret this implied Q4 guide. It feels quite conservative, and then I have a follow-up.
I will answer this, this question. Yes, I, I would say I agree with you. It's a conservative guidance for this year with this EUR 1.7. We are very confident that we will achieve, and it will be sure EUR 1.7+.
Okay. No, brilliant. And secondly, just on the FY 2027 guide, actually, whilst I have you, so again, that's been reiterated. I remember you stated in your report, I think in Q1 or Q2, that you have shifted your expectations from the high end to the lower end of the guide due to FX headwinds. But I think, you know, more recently, again, like I said, we've seen positive pricing developments in the last few weeks or months in ABF substrates. People are talking about ABF substrate pricing being up potentially 15%-20% in 2026. And you also added in your report, interestingly, you know, that customer forecasts are being revised upwards for the second half of 2027.
You know, could the high end of the 2027 guide be within reach, or are you still sticking to the low end, basically?
I take also this one. I told it, I think in the last quarter, our guidance was calculated with euro or US dollar from 1.07, and we are now at 1.17, 1.18, even we have last week 1.20. So there's a lot of headwind in the FX. And the second point that we see is also the S-glass shortage here. Even if there are demands, we have to see if we can then fulfill everything, you know, so that we stay with the lower end.
Perfect. Thanks, guys.
Thank you. The next question is from Daniel Lion from Erste Group. The floor is yours.
Hi, good afternoon. Thanks for letting me on. I would like to follow up on next year's guidance. Can you give us maybe a little bridge in terms of where you stand now, in terms of capacity, utilization, and capacities itself, and to what extent you will need to other capacity ramping up in order to meet the guidance? Just to give you some insight where I come from, you know, Delta is 350 at least, or should be 350-400 if you exceeds the EUR 1.7 billion for full year. So, where should it come from, and how you think about additional capacities here?
Yeah. Sorry, Daniel, as Silvo already answered, I will take this one. You will get the IR answer. Well, that's an additional capacity coming out of Kulim. So we are in the middle of the ramp, in not technical terms, of having the CTO next to me, I have to be careful, but just add another line, and that brings you the revenue into the EUR 2.1, up to EUR 2.4. Don't forget also Hinterberg contributing to this, but really, the big change in the setup is more capacity out of Kulim.
Okay. And maybe a second one also somehow relates to this. When you look at peers announcing already additional capacities, substrates, you know, to live up to increased market expectations or market demand, how would you think now going forward in terms of CapEx? You level down to EUR 200 million for this year. Obviously, free cash flow, due to free cash flow reasons, but how should we think of next one or two years? Would this be a level that is reasonable, or would we have to add maybe the lower CapEx this year to CapEx in the coming two years, maybe?
Yeah, I think the lower CapEx that you see in the Q4, or will see in the Q4, compared to what we planned for full year, is, of course, again, as every year, a bit of a timing difference. So we're shifting it a bit into the next year. Whatever is possible, so you can add it to whatever you expected for the maintenance next year, and the additional line might be a bit higher than what we said a year ago. When it really comes to the big expansions that we heard from competitors in the recent hours, I think that is something that we have to look in very carefully, and we will announce whenever there is something happening there.
Okay, thanks.
Thank you. Next question comes from George Chang, from Aletheia Capital. The floor is yours.
Hello. Hi, just a couple of questions. First of all, what are the considerations for the ASIC clients when they choose between CoWoS and EMIB, EMIB T?
Well, it's technology-wise difficult to say what really drives one in this direction, what drives one in the other direction, because both of these architectures have their own, their own benefits. It is also traditionally, when you have bought from TSMC, you only get CoWoS. If you have bought from Intel, which very few had in the past, then you get EMIB. Only recently, Intel opened up for EMIB. When they decide now, what you probably will assess is the overall, the total cost for your package. That could be going forward, in particular, when the size becomes bigger, there could be a significant difference. Other than that, that's a question that's better answered by the package designers than by the substrate manufacturers.
Okay, great. The other thing, I just want to just verify is that my understanding is that the capital intensity for EMIB T is probably double of that regular substrate. And, you know, it sounds like it's a lot more than traditional the EMIB. So I'm wondering, can you explain sort of the why EMIB T investment is so expensive?
Yeah, it is. Well, is it expensive or not? That is in the, everyone might have a different judgment on that one, but it is more expensive, capital-wise, definitely, to build an EMIB compared to a standard substrate, because one of the reasons is the precision that you need to exhibit when you assemble the die into the cavity of the substrate. That precision is semiconductor-level precision, talking about micron, 1 micron, 2, 3 microns. And when you go from EMIB, where you have a single side connection to EMIB-T, where you also connect from the bottom side, all of that becomes even more tight. The tolerances are going down, and the process steps are going up.
Because connecting from the bottom side, in a, in an architecture where you have the die, not in the center, in the core of a substrate, that is a complete unique process that requires a lot of additional process steps that make the whole process more expensive, the investment bigger. But, whether it's twice as much as a normal substrate, that remains to be seen. I would challenge that.
Thank you.
Thank you. The next question comes from Lucas Nikas from Mizuho Bank. The floor is yours.
Yes, hello. I had the same question, but as for my colleague, so thank you. I'll pass this on.
Okay, thank you. Then we have the next question from Gustav Froberg from Berenberg. The floor is yours.
Great. Thank you very much for taking my questions as well. I just have three, please. Just looking at the slide on the contribution from new customers, I'm just wondering from which facility or where are you intending to serve them from? And do you have sufficient space in your factories considering current customers as well, to serve new customers at volume? Question one. Question two, a technical one, just on CoWoP. Does this not disrupt the business that you have in Kulim and Chongqing, thinking that there's no package substrate involved at all? I'd be very curious to hear your view there. And then lastly, on EMIB-T as well, are you EMIB-T ready in Kulim?
I know there's a lot of talk about the future there, so just wondering if you're fully ready to start manufacturing EMIB-T packages, or if you need to invest anything further to get ready for that type of technology. Thank you.
I take the first one regarding the new customers. Everything is linked to Kulim. The second one was white space. There is white space, and so there we can put additional things in. It's possible.
Then the question regarding CoWoP, and will it be a challenge for our business? Well, we cannot ignore it, that's for sure. However, will it come? Will it come in the way it is intended now? Will it be for a niche of products? And which customers are going even for that kind of architecture? It all remains to be seen. That won't happen from today to tomorrow. There are not even capacities in the world that can manufacture that kind of PCB or SLP or however you want to call that thing. That would take time, a lot of time and massive investments going forward, if that should really spread out across the whole industry. So let's see where it goes, and we will observe it very carefully.
We will make our preparations to be ready when it's needed. The third question was about-
EMIB-T.
EMIB-T in Kulim, whether this is requiring additional, in investment. Well, yeah, generally, Kulim so far doesn't have EMIB-T capabilities installed. So if we want capacity there for EMIB-T, it definitely will need a certain amount of investment.
Okay, super. Thank you.
Thank you. We have the next question from George Brown from Citi. The floor is yours.
Yeah. Hi, guys, again. So two more questions from me. I can take them one at a time again. Just thinking about Kulim and the second plant you have, which is effectively a shell today. In the context of capacity utilization at your peers, already sort of nearing 100%, and, you know, a lot of capacity being increasingly absorbed by the likes of NVIDIA, you know, is it likely that, you know, Intel or other customers are looking at K2 with more interest today? You know, especially if you consider Intel, the roadmap for EMIB as more external demand, but, you know, these substrates are becoming much larger, higher layer counts, which obviously absorb much more capacity today relative to, you know, five years ago.
Should we expect any developments in this regard for K2 over the next sort of 12 months or so?
Yeah, very good question. Feel a bit reminded of Daniel's question. If we would consider there's something or the management board would decide something in that direction, of course, we will let you know ad hoc right away. Let me phrase it that way.
Okay, perfect. And then just maybe a technical-ish question. On the vertical power opportunity, thanks for highlighting. It seems very interesting.
I assume you're working with, you know, big, big players here, whether that's Infineon. Yeah, Infineon, they've, they've outlined quite a big TAM, I think, for vertical power by 2030, within the sort of EUR 8-12 billion mark. You know, do you have a sort of figure in mind as to how big this opportunity could be, could be for you guys in the 2028-2030 timeframe? You know, as I assume, as you shift from lateral to vertical power, you know, you're shifting towards embedding more components within the substrate, so the complexity is going up. I assume you, the, the substrate share of value is also going up as well. So, so any sort of data points to share there could be helpful.
I think your considerations are all correct. The value adding for the substrate must increase if we embed active or passive components. But giving a concrete figure at this point in time, I'm not in a position to do so.
Okay. No worries, guys. Thank you very much.
Thank you. So if you would like to ask a question, please press nine and star on your telephone keypad. We have one more question from Daniel Lion from Erste Group. The floor is yours.
Yeah. Hi again. Can you maybe provide us also an update on glass substrates? Has anything changed in your perception? The market is still some time away from implementing such a technology?
Yeah, right. Glass, glass substrates have gone through the whole hype cycle. Intel starting 2.5 years to trigger the hype. Everyone was talking about it, and then Intel was also the first one to become quiet about it. And in the meantime, I think a sort of realism has come into that, that glass is not a simple thing to introduce. In particular, the fracture mechanics of glass is not enough studied to ensure enough reliability. And so while a lot of companies are working on it, a real introduction in high-performance computing seems still to be out some years. And Intel said in the second half of this decade. Yeah, let's see if we can really make it in that decade.
That is the perception I have from the market at this moment in time.
Thanks. Perfect, and then a question to speakers again. How would you expect the cost-cutting program impact your profitability going forwards? How much of this EUR 160 million that you mark this year, savings target that won't be? Would you expect to see converting the cost savings next year?
Let's say the program is a sustainable program, so our expectation is that most of it will go also in the next years. But I cannot tell you now a number. That's but the most portion should be sustainable, is my view on it.
Okay. Thank you.
Thank you. We have some more questions from Frederick Dyer, from Town Square Asset Management. The floor is yours.
Hello, thank you for taking my question. I just wanted to ask if you can elaborate a bit around your plans with your hybrid capital, please.
It's difficult because I can tell you that we evaluate on a hybrid, and as you should know, I have to go then. I talk if it will come to it. And we have a little bit time because it's until January, so. But we will inform then the market.
All right. Thank you.
Thank you. We have one more question from George Chang, from Aletheia Capital . The floor is yours.
Hi, thanks for letting me back again. Just one more question on the CoWoP. So you've talked about, let's say, the challenges for CoWoP. Can you just give us more details on, let's say, the technical challenges for CoWoP? Because then my understanding is that the line space for IC package is already about 5 micrometer, whereas mSAP is still probably about 20/20 or 15/15. So how do you close that gap between the two?
That's a good question. Something we also scratch our head, how the package designer will overcome that. Either you need to introduce an SAP-like processing, and get down with your line space to 8 micrometer, which is the typical space that line space that you need currently for most of, of the, of the substrates... or else you'll probably get stuck with around 15 micrometer line space and mSAP, which would be easier to handle for the manufacturer of this CoWoS thing. But then you need to transfer some of the complexity upwards to the still remaining silicon interposer, or whatever the interposer will be made of in the foreseeable future. So one of these two directions needs to happen. I don't think the judgment is out, which way it goes.
That's as much as we can say at this moment in time.
Great. So in terms of, let's say, you know, the timeframe development, it would be probably as an EMIB-T first, and then maybe CoWoS sometime down the road, like 2033 timeframe?
I can't give you any concrete number. Even I believe, in all honesty, even the customers themselves would not know when and with which product they are going to intercept that kind of technology. As the fundamental technology bricks to solve all the issues that come with warpage and coplanarity, and God knows what, they are still not completely available, tested, and the whole system proven that it can work that way. So you need to give it a little bit more time to go through all the necessary testing until anyone will dare to give you a concrete date for the implementation of such a technology.
Thank you so much.
Okay, so as there are no further questions, we will conclude today's conference call. Thank you for your participation and questions. If you have any further questions, please feel free to contact the IR team, Johannes Mattner, and me anytime. Thanks again, and goodbye.