All right, good morning. Let's go ahead and get started. Welcome to the second day of JP Morgan's 52nd Annual Technology, Media, and Communications Conference. My name is Harlan Sur. I'm the semiconductor capital equipment analyst here for the firm. Very pleased to have Anirudh Devgan, President and Chief Executive Officer of Cadence Design Systems, here with us today. Cadence, leader in electronic design automation or chip design software and hardware solutions that help semiconductor companies bring their most advanced chip SoCs to the market, and Cadence is also a leader in the emerging area of systems design and analysis solutions. Now, so Anirudh, thank you for joining us today. Before we get started, I am gonna read the team's safe harbor statement. Today's discussion may contain forward-looking statements, including Cadence's outlook on future business and operating results.
Due to risks and uncertainties, actual results may differ materially from those projected or implied in today's discussion. All forward-looking statements during this meeting are based on estimates and information available as of today, and Cadence disclaims any obligation to update them. So with that, Anirudh, again, thank you for joining us today. Maybe to kick things off here, and for those of you that may not know Cadence that well, the team is an enabler and a beneficiary of three major trends, right? First, you've got significant growth of leading-edge chip designs targeted at accelerated compute and AI. Two, the move of semiconductor customers from developing chips to developing systems, right? And number three, the move of your systems OEMs and hyperscalers from developing systems to developing chips.
Maybe you can summarize how the portfolio of solutions at Cadence addresses all three of these trends?
Yes. Thank you, Harlan, and thank you everyone for your interest. So, like Harlan mentioned, we are basically a software company, and what we like to say is computational software. So this is not your regular software. This is more mathematical, numerical software. Because these chips are too complicated to be designed by hand, and they haven't been for a long time. So they're mostly designed by, you know, Cadence. So what we say is almost any chip design in the world today uses some form of Cadence software. Okay. And then the growth drivers, like Harlan mentioned, there are several of them. The three big ones are. So right now, about 55% of our revenue is from what we would call semiconductor companies, and 45% is from system companies. And semiconductor itself is in a big renaissance, as you know.
So, right now, the semiconductor revenue is roughly, you know, $500 billion or so, going to, is widely projected to be $1 trillion-
Mm-hmm
... by end of the decade, and, you know, I think that may prove conservative. It might reach there before that. So there's a lot of growth in semiconductor design anyway, and I think the, the big drivers, as you know, about going from $500 billion to $1 trillion, there are at least, you know, two big drivers. So one is, all this AI and data center demand, and then the other is definitely automotive. You know, we can talk about that. So, so those are multiple hundred billions each, right?
Growth drivers, and then all the other edge devices, consumer devices that may have. So we are, you know, we are glad to participate in all that, so there's a massive growth in, semiconductor content. You know, a good example is, like yesterday, this announcement by, Qualcomm and Microsoft, and, you know, Cristiano was at our Cadence conference a few weeks ago.
Yes.
So we have a long history working with Qualcomm and all their advanced CPUs, and also a history working with Nuvia, which Qualcomm acquired, which is the basis of this, Snapdragon X Elite. So it's really good to see that, you know, AI coming to the edge and disruption in that kind of market, and in a lot of other kind of semiconductor. And, of course, we have a long-term partnership with NVIDIA we can talk about, and Jensen was also there at our Cadence LIVE-
Mm-hmm
... conference a few weeks ago. So, that's the semiconductor part of our business, and also, these companies, like NVIDIA and Qualcomm, a perfect example, they are not just semiconductor companies anymore. They are almost like system companies.
That's right.
Yeah, with massive software stack, firmware stacks. And the second big growth for our business last few years, which is expected to continue, is system companies doing silicon. Okay, and of course, it started a few years ago, you know, almost 10 years ago, by the big mobile companies-
Mm-hmm
... doing it, and they kind of led the path of doing silicon, and they're phenomenal in their own way. And then last few years is all the data center and automotive companies. So I think this is public, this is fairly public, all public information, that all these big data center companies, whether in the U.S. or outside, you know, like, are all doing- have massive silicon investments. And same thing true in globally, right?
Right.
Yeah. So that's a big part of, that's what is, like, what we would call the 45%.
Yep.
That's also growing well, and I still think that's in the early innings-
Mm-hmm
... because there's still a lot of things to be done in AI and also automotive and other kind of mobile. So that's the second part of our growth, and we can talk more about that. And then the third part is we are expanding our TAM anyway. So as we, you know, work with these system companies and semi companies, you know, our traditional suite is EDA and IP-
Right
... you know, chip design software. But, like, even NVIDIA, you know, they talk about not just designing the chip, designing the data center... or, you know, not just designing the phone, designing the mechanical part of it. So there is a convergence between electrical and mechanical design that is happening for a long time, and I think Cadence is the first one to recognize this, you know, in 2017, 2018. So we have a new category, what we call in sort of EDA, SDA, System Design and Analysis, and that's growing, you know, 20%+ last several years. And then even this year, we announced, like, partnership with NVIDIA to do data center design-
Mm-hmm.
and then some other tools for, you know, car design, you know, with McLaren and Honda. So that's also a good growth business for us. That's about a $10 billion TAM for us-
Yeah
... and we are, like, you know, $500 million-$600 million, so there's a lot of growth opportunity there. So those three would be the kind of systemic growth drivers, which should continue for the next five to 10 years. And then coupled with that, we are always very disciplined financially, so we have, you know, very good financial performance margin. We always focus on that EPS growth. But at the same time, we have the highest investment in R&D. So we have about 35% of revenue invested in R&D, but at the same time, have very high profitability, so.
No, that's great.
Mm-hmm.
And we'll get into all aspects-
Mm-hmm
... of that through our discussion here. I do wanna start off with the core sort of chip design software-
Mm-hmm
EDA business, right? We do our best to track and chip design activity, primarily with the large ASIC semiconductor companies, right, that are helping hyperscalers and systems companies co-design their custom chips, because we think that they're a good proxy for just overall sort of leading-edge chip design activity. And chip design starts have accelerated just over the past 18 months, right? Given that there's this AI arms race amongst these cloud and hyperscale titans and off-the-shelf guys like in NVIDIA, they all wanna bring their leading-edge silicon solutions to the market sooner rather than later. How is this acceleration in leading-edge design starts manifesting itself in terms of how you see the growth outlook for your business, not just this year, but over the next several years, right?
Does it just provide you with confidence on driving to your low- to mid-teens type revenue growth target, or do you think about it as a SAM expansion opportunity that can bias the growth towards the upper end of the growth range?
Yeah, that's a good question. I mean, there is gonna be a lot more silicon design-
Mm-hmm
... next few years, right? Even like our foundry partners have commented on, like, how much more design activity, as you know, is at N3 or 3 nm versus 5 nm or 7 nm. And AI-
2 nm, right?
Exactly. So we are working on 2 nm for some time already, you know, several years already, because some of the early customers are already designing at 2 nm, and most of our R&D with, like, TSMC or the fabs, like Samsung, Intel now, switching to 1.4 nm.
Yeah.
Okay. So one good thing is that, you know, we are at 3 nm, so there is 2 nm, 1.4 nm, and 1 nm, so that's at least three more nodes. So there's at least, you know, eight to 10 years of Moore's Law that we can see right now.
Yes.
Each node requires bigger and bigger chips because, you know, the Moore's Law may have slowed down in terms of performance. Because one question always is, okay, well, how much room is there to keep this semiconductor? But in my viewpoint, it's at least 10 years of pure scaling.
Yeah.
Okay, and whenever you have pure scaling, the performance may not improve as much as in the past, but the area scaling is there. So when you go from 3 nm to 2 nm, you know, there's a massive area scaling. So that means more things can be put on the chip, right? And then all these chips have to be designed, and they always need more software from Cadence, because the design effort is roughly proportional to, at first order, proportional to chip size, even though the chip complexity also goes up. So if you look at from now till 2030, and the way I look at it, you know, right now, the chips are 100 billion-200 billion. You know, Blackwell have 200 billion, but most of the other chips are 100 billion. And it's widely projected by 2030, they will be 1 trillion-
Yeah
... okay, to answer your original question. So that is at least chip size will go up by 10x, you know, next five, six years, but the chip complexity will go up more than that-
Yeah
... you know, with the software, and also, it's not just the size. They have more cores, more GPUs. You know, the complexity of and verification of the chip goes up exponentially with size. So the chip complexity, the design may go up by 30-40x from now till end of the decade, and it's not possible for our customers to hire, like, 30-40 times more engineers. I mean, they will hire more engineers, but there's not even enough engineers graduating, you know, that can be hired 30-40 times more. But I think they will still hire more. So let's say there are two to three times more engineers.
Mm-hmm.
So then there is a 10x productivity gap that has to be made up by better software and better compute, and using AI in our own tools. So I think the real opportunity for, for Cadence and the industry is that from now till end of the decade, the more of the R&D can go to automation, rather than what has done in the past. So even if you look at EDA spend now, as percentage of R&D has improved in the last five-
Yes
... 10 years, but there is opportunity to do a lot more in the next, and that should help in terms of, you know, our, our top-line growth.
And that's a good point that you bring up, right? Because on one hand, your solutions help NVIDIAs, and Googles, and Broadcoms of the world bring their most sophisticated AI chips to the market. But then, in return, you need the compute power-... and also integrating AI capabilities into your own set of solutions-
Mm-hmm, mm-hmm.
Right, in order to boost sort of productivity. The team has been developing and integrating AI and machine learning-based methods across your entire portfolio, right? For digital implementation with Cerebrus, verification with Vericium, and even into your system design and analysis portfolio. Talk about the use cases and adoption of your Cadence AI solutions portfolio, and any metrics that you can share with us in terms of adoption curve.
Yeah, absolutely, yeah. So first of all, you know, one thing you have to be careful, you know, these days, everybody calls everything AI. You know, that's another issue. But, you know, like I said, we have been doing this computational software for a very long time, right? You know, the history of EDA is over the last 30, 40 years, is this kind of mathematical software. So we have done all kinds of automation over the years.
Mm-hmm.
You know, AI is another way to, is another significant way to provide that automation. But even if you go back, like, 20 years ago, you know, a chip would take. You know, I remember, like, these big chips at that time would take, like, four or five years and 400 or 500 people.
Mm-hmm.
Okay. These days, you can do it by, you know, like 50 times or 100 times easier than that...
Right
... both in terms of time and people. And I think the foundry ecosystem has played a role in it, and you know, our software has played a role. So it's much easier to design these chips than 20 years ago. That's why all these system companies are doing it now. But there is still more room to go, and I think the one thing that we never did before is, you know, if you go to our customers, they design, they're running our software on a daily basis. But, they're you know, we, our software was mostly what I would call, and all software, was more single run. That is, you give it an input, and it runs for one or two days and gives you a very good output.
Right.
But the design doesn't happen in a single run, right? Typically, what is happening in these, all these big companies, you know, the designers, they are, they run it, they change something, they run it again, they change something, they run it again. Okay, this is what happens over six to 12 months to design one of these chips. So, so we never provided automation in that, the workflow automation. Not, not that we didn't want to provide it, but there was no mathematical way to transfer the learning from one run to the next run. Okay. But now with AI, with real AI, okay, not, not- you know, a lot of times people will call simple automation AI, but what we would call real AI or-
... you know, gen AI or real-world reinforcement learning, we can actually model what the human is doing manually into an AI model, and we can automate the workflow. So that's how we have applied these-
Yeah
... AI techs. And I can give a lot of examples, but it, what that does is it can shorten the time, you know, design time, but more so that's a productivity improvement, you know, which is well known from AI standpoint. But I think what is more interesting to me is that it can give a better design. To give you example, you know, one of our customers is designing a automotive CPU, and they are changing a lot of things. In that case, they were changing 17 different variables. You know, some of them are design variables, some of them are process variables, some of them are power options. So you do the design, it takes you six to 12 months, but you're doing it by human intuition, right?
Mm.
You know, "I used to do this before. Let me try this, try this." So even though our tool, Innovus, is very complicated, the driving of that tool is done manually. But with AI, we can do it mathematically, so it can give, like, 5%, 10%, 15% better PPA than a human design. Depends how good the original design was, but that's remarkable. So PPA stands for power, performance, and area. So we have, like, 8%, 10% better power.
Okay, that's, that's like huge compared to when you go from 7% to 5% or 5% to 3%, you may be getting 10%-15% PPA improvement with massive investment, and you're getting, like, roughly that or slightly less than that with better software. So there is a huge value in automation and also PPA improvement. So, so we are applying all kinds of AI techniques to improve this whole workflow from a single run to optimizing the search of the design space. Yeah.
In terms of productivity gains right, hardware verification, emulation, prototyping, this has been a big contributor to the team's double-digits growth profile. Here, you're essentially creating a digital twin of your chip design on a high-performance compute cluster. You're accelerating verification efforts and also getting a head start on the embedded software design that will eventually be running on these chips, right? 10 years ago, these hardware-based verification systems were sort of a nice-to-have, not necessary, but given the sheer size of current-generation chip designs, the usage of hardware-based verification and emulation is now mandatory, right? You're also at the start of an upgrade cycle with your next-gen Palladium Z3, Protium X3 platforms, with a strong near-term demand profile.
But I think the investor question comes up, you know, after three strong years of hardware sales, will customers have enough hardware and compute, emulation, and prototyping performance capacity, or does the team envision continued growth beyond this year, just driven by sort of the sheer increases in chip complexity and software development?
Yeah, that's a good point. So I'm super excited about the new hardware. So I mean, we are a primarily software company, but just so for people who don't know, we do sell some hardware products, and this is to help the design process. So what happens is, NVIDIA is a great partner and a public, you know, supporter, so I can talk about NVIDIA. Good thing is like I say, Blackwell is announced, the chip comes back, but all the software is also available at the same time. Okay? So this is a new change in the last few years now. NVIDIA has been doing it-
Right
for a while, but now everybody else is, in which hardware and software development is overlapped. So in the past days, like you know, 20 years ago, you would do hardware development, and then you would do software development, and then the chip would, you know, system would come out. But now it's overlapped, so hardware and software is developed-
Mm-hmm
-in parallel.
Mm-hmm.
So when the chip comes out, you know, three months later, you can buy it from Supermicro or whoever your favorite, you know, vendor is, and everything works, right? So the only reason that's possible is when you're writing software, and all these system companies are writing software, and semi companies, there is no chip. So we have a product called Palladium that will mimic as if the chip exists.
Right.
Okay, it will mimic it, like, thousands of times faster than general purpose hardware-
Yeah
... like CPUs-
That's right
-or something. So then it became like an essential part of the design process. It's almost impossible now to design any of these complex chips without having emulation on Palladium. That's why, you know, of course, Jensen was saying it's more important to him than a refrigerator or, you know-
I think when he came on stage, what was his first comment? "I love Palladium. I need more Palladium."
Yeah.
Right, isn't that what he said to you?
It's great, you know, NVIDIA is a, is a great partner. I think he publicly said that design of Blackwell was, would not have been possible without Palladium. And this is true for all the other kind of-
Yeah
... chips as well, and big chips. So this is happening for a while already. Now, what happens is, as the chips get bigger and bigger, and then you have more software running on them, the need to verify these things also goes up exponentially.
Yeah .
So where we sell Palladium is, for example, and this is, it also was talked about, so, like, NVIDIA, which is Blackwell, which is one of the biggest chips in the world right now, is 200 billion transistors, okay? And it's most of it is logic. You know, so GPUs have more logic than a CPU. Like, you have a CPU, could be 100 billion transistors, but a lot of it is memory. So in emulation, you know, it may require less capacity. But GPUs always, not only they are big, but they have more memory.
Mm.
Okay, so, so Blackwell is about 200 billion transistors. It was emulated on eight racks of Z2, which is our previous product. Okay, and now with Z3, which is our new product we just announced in April, we can go to 16 rack of Z3, so that's about 5 times bigger capacity than Z2. So we have the ability to now emulate chips with one trillion transistors, okay? Which is huge, and so that should be good for the industry for, you know, at least for next several years, several generations. Even a partner like NVIDIA said they can use Z3 for several generations of next generation GPUs, and then the other industries. So this is a big jump. Now, the question is, how—what does the demand look like-
Right
... these systems like? So first of all, even with the transition year, this year, I expect to have every year we have had a record year, like you mentioned-
That's right
... in our hardware business. So I, at this point, I do expect, you know, 2024 should be a record year also. Our guide is fairly, we are not assuming a massive growth in the functional verification business, which hardware is part of, but it still should be record than-
Right
... last year. And of course, we are not guiding next year or year after because we are pretty, you know, conservative in those things. But historically, a new refresh should add to future growth.
I see.
And then what happens in these things, so like I was telling earlier, what's gonna happen for next 10 years is, there's going to be this Moore's Law, you know, this 3 nm to 1.4 nm and 1 nm. Okay, and on top of that, there would be this 3D- IC. Even Blackwell or-
Yep
... even Intel's latest chip or, you know, Amazon, they're all multiple chiplets on a die, on a package, right? So it's no longer limited by the reticle size.
That's right.
Even Blackwell has, like, two full reticle.
Mm-hmm.
And so the actual capacity of the system, whether it's a single chip or multiple chip in a package, is gonna go up exponentially in the next five, six years. Okay. It's just because of, you know, the Moore's Law scaling, you add 3D- IC to it, and it's all driven by the demand of more compute and whether it's in self-driving cars or data center AI. So the bigger the chip gets, you need more emulation capacity. Because these things, when we sell Z2, Z3, is based on how many gates it can emulate. So if the number of gates is 10 times bigger, you need much more emulation capacity, not only for it to fit the design, but also as the chip gets bigger, it has more verification to do, exponential more-
Right
... corner cases to. So the verification demand should go up, which translates to hardware demand and also our software demand. So I mean, we'll see how it goes, but you know, fundamentally, there is a lot of reasons that this should continue for some time. Yeah.
Let's talk about advanced packaging, right? You know, the adoption and acceleration of AI and accelerated compute has really driven a push towards things like high-bandwidth memory, 2.5D, 3D packaging, right? All of the leading-edge chip companies are moving to these type of architectures. It's a way to, like you say, continue to drive Moore's Law-like performance scaling without having to rely solely on semiconductor process technology scaling, right? Here, the Cadence team benefits with, for example, Allegro X and Integrity platforms for design implementation of advanced packaging and PCB, right? Celsius for the thermal analysis and your verification tools. But advanced packaging also pulls a lot of critical IP, like chip-to-chip connectivity portfolio, and so on.
So can you just update us on, if we take all of that under the umbrella of advanced packaging, help us understand the revenue contribution, momentum of your solutions targeting the advanced packaging segment of the market?
Yes, Harlan. So this is actually one of the reasons that we did this whole, like I was talking about in 2017, 2018, we moved to system design and analysis. And the reason was, there are a couple of reasons. One is that, you know, of course, we have the pleasure of working with all the leading companies in the world, so we do know what is happening.
Mm-hmm. Mm-hmm.
Okay. And so on the chip side, but at the same time, you know, Allegro is a long-term Cadence product, like almost 30 years, and is the most advanced tool used for packaging. So in advanced packaging, that's the most common tool used. Okay. And, you know, even in the 1990s, there was all talk of, you know, interposer and all that.
Yeah, right.
Even when I was in IBM we used to talk about it. Then when I joined Cadence almost 10 years ago, we worked with TSMC on a 3D-IC flow.
Mm-hmm.
Okay. But it didn't go as well, you know, 10 years or whatever, eight years ago. But last few years now, this is a resurgence of, because technically, the industry has always known the way to one other way to solve scaling is putting not just system on a chip, but system on a package. You know, like, putting more chips in a package gives you scaling, just like, you know, Blackwell, you know, even if, even though each chiplet is huge, you can have two of them and then bunch of HBM, right? So it gives an orthogonal dimension to Moore's Law, like you're saying.
Yeah.
And now look at TSMC, they're investing a lot, and, you know, Samsung, Intel, GlobalFoundries, and all the memory players. So Cadence has a unique position because we are the leading packaging, advanced packaging. Actually, the format that is used to manufacture advanced format is Gerber format, which is a Allegro format. So I always know for a while that we need three big things to solve this problem. So, at the lowest level, or like three-layer stacks, at the lowest stack is, of course, chip design tools. So we are the only company that has both analog and digital chip design tools. So this is Virtuoso for analog, and Innovus-
Yes
... for digital. Because some of the chiplets are purely digital, some are analog, they're mixed signal, you know, that's the whole... And then the second layer of that stack is we need package design tool, which Allegro and Allegro X is the main platform in the industry. And then the third layer on top is you need analysis tools, like thermal analysis, stress analysis, even like stress, mechanical stress, because, you know, HBM has eight layers of memory going to 12 layers of memory. There's all kinds of mechanical stress that happens. And thermal, you know, TSMC and other foundries have talked about thermal being a big issue. So that's why in 2018, we launched all these analysis tools, SD&A and all that. And if you put it all together, that's what we call the Integrity platform-
Yeah
... which is probably the most complete and successful platform for 3D-ICs. And, you know, when TSMC launched in October of 2022, you know, this latest round of 3D-IC, which is very, very successful now, you know, we have big partnership with TSMC on, on 3Dblox , and then also now with, with Samsung, with Intel, GlobalFoundries, and all the... So this is gonna be a big thing. I mean, and we can talk a lot about it because there are a lot of benefits to this. You know, even like, take example, like some of these hyperscalers, like this is all, all, all well known, like Amazon launched-
Mm-hmm, mm-hmm, mm-hmm
... Graviton a few years ago. It has like six or seven chiplets on a package. So it started with HPC, you know, high-performance computing, which is, you know, the AI or even, you know, CPU compute. You know, Graviton was a CPU chip, and then there is the AI chip. But I think this disaggregation is moving throughout the industry stack. So Intel launched Meteor Lake, which is, you know, laptop chips. That's disaggregated. And then it's happening in auto, it's happening in other markets. So I think this is gonna be a big wave, and Cadence is very, very well positioned in this area. I mean, some of it is good planning, some of it is we had Allegro for a while, some of it is, you know, working with the latest foundries, so... But this is gonna be a big thing along with regular Moore's Law scaling.
Yeah. You know, you talked earlier about the mix of your customer base, right? 55% is classical semiconductor companies, 45% is systems, hyperscalers, and so on, right? And again, like, we've seen so much more announcements. Obviously, we're familiar with, you know, NVIDIA, Hopper, Blackwell, AMD MI300, but in fact, we've actually seen more product announcements from the cloud and hyperscalers that are doing their own custom, what we call ASIC designs right?
Google TPU, Amazon, as you mentioned, Graviton, Inferentia, Trainium, Meta, MTIA, ASIC programs, and so on, right? So it seems like the hyperscalers, large OEMs, continue to be gravitating more and more towards wanting to do their own custom solutions. So can you just give us an update on your systems and hyperscale customers, right? Are you seeing the design activity accelerating within this customer base, and does the contribution mix from these customers actually you see rising over time to maybe 45%-50%, maybe even half of your business?
Yeah. I think the question always is like, okay, are system companies doing silicon, is this going to continue?
Mm.
Or is it going to accelerate? Is it going to slow down? I mean, this is always a question because, you know, is it too hard-
Right
... or is it not, is it too easy? You know, there's always the... So what I would like to say is that... the, what I found over the last several years of why do system companies do silicon, okay? And this, you know, this mobile company is a perfect example, or, you know, like-
Yes
... Tesla is a perfect example. So, I found that three reasons they do it. So, first reason is, it's a domain-specific product.
Mm-hmm.
So it can do some things better than a regular standard product cannot do. Like in case of Tesla, I mean, the power consumption was lower, and Tesla has their own chip for FSD, right? Or, you know, when, you know, these M-series chips came out for laptop, it's quite remarkable, right?
Mm-hmm.
Your laptop battery was the whole day, and the laptops were so thin. You know, that's why you're seeing now Microsoft and Qualcomm-
Yeah
... kind of follow what was started by, you know, by these M-series laptops. So there's always some unique domain-specific differentiation that happens, so that's one reason. Second reason is to control the schedule and the supply chain. You know, because if you're a huge system company, you know, you're gonna launch certain amount of products, or you have some schedule, you want some control over that, so that's the second reason. And the third reason, which is often, I think, not fully understood or not as talked about, is that if there is enough volume, because there's this, this is, you know, you have to put the effort to design these chips, but if there is enough volume, it is actually can be cost-beneficial for the system company to do it.
Yeah.
You know, because and what is that volume? It depends on each application, how much it costs. But definitely in AI, there is volume, and volume is growing. You know, in mobile phones, there is enough volume. Volume is in laptops, there is enough volume. In cars also, there is enough volume. So I think, so for those three reasons, I think this is going to continue. Now, there will be, you know, some, you know, not every system company will do it, but right now, not... You know, AI, it's happening, more and more are doing it, but automotive, there is still more can happen. And then also what happens typically, and you can look at the, you know, history in mobile, that typically the company will do one or two chips first, make sure it's successful, then they expand to more and more chips.
You're seeing that with even in hyperscalers like, like Google.
Mm-hmm.
You know, they did, like, a TPU, then they do like a YouTube chip-
Right
... essentially, it's quite remarkable.
Right.
You know, YouTube loads much faster, and then same thing happened, like you mentioned in Amazon. And then also, they will, in the beginning, do some part of the chip, and then they will do the whole chip. Like, in the beginning, they may use, like, a ASIC partner, and then they may try to do more in-house. So there are a lot of trends that are in that direction. And then the question always is: Okay, what is going to be the distribution between, like, standard products versus in-house products?
Yeah.
Okay, and it's very difficult to predict. You know, there will be some mix, and I think that’s more from a Cadence standpoint, you know.
You win either way.
They have to be designed.
Right.
So as long as there is financial reason, of course, for our semi companies to, customers to do it, they should, and for the hyperscalers, and the system companies, and the mobile companies to do it, which they will, so we are glad to support both of them. Now, what will be the actual distribution or what percentage? I mean, that's we leave that for the customer to decide and the market to decide. But our job is to support both fully, and we are glad to do that. Now, whether system will become a bigger portion, see, it moves very slowly because the semi is going to do so well anyway.
Yeah. Yeah, that's right.
You know, look at, you know, Qualcomm, NVIDIA-
Right
... all these, you know, Broadcom, I don't know what, whether you call them semi or-
Right.
I think normally we, the good thing for us is that both sides are growing. The semi is growing, and the system is growing. Yeah.
We're just about out of time but I do want to ask a question on the systems design and analysis way, because this has been a strong outperformer from a growth perspective. Right? Up 22% last year. You know, outgrowing the overall market, it's set up to grow faster than your corporate growth rate this year. As you mentioned, right, the Cadence team was actually the first amongst your competitors six years ago to acknowledge this trend towards more subsystems and systems-level design, even by your semiconductor customers.
Since then, you've been building, you know, scale, a portfolio, organically and inorganically. Like, it's gonna drive $550 million-$600 million in revenues this year. With your EDA competitor setting up to potentially acquire Ansys, how, how is the Cadence team gonna step up to its efforts to build, scale, drive growth, and maximize the synergies between your chip design and systems design and analysis segments?
Yeah, we are very well-positioned. I mean, I think the other people are trying to react to what we did like, six years ago, so there's no need to react to the reaction, you know? So we, you know, we are very well-positioned in the sense that, you know, we are competing well with them individually.
Mm-hmm.
So if they combine together, I mean, I don't think that changes the competitive landscape in any big way. And also, it's still, like I was talking about in 3D-IC, you know, analysis is important, chip design important, but the packaging is super important.
Right.
So we are still pretty differentiated in terms of analysis, still very differentiated because we have the broadest EDA portfolio with analog and digital. Then, of course, we have a critical piece of packaging that drives 3D- IC.
Yeah.
I feel pretty good in terms of our competitive position, and, you know, the customer response has been very good. You know, the investor response has been very good. You know, also, we have a good financial model, which is not in any, you know, which should continue next several years. There is no kind of overhang of a large acquisition and things like that. So, see, we are more, focused on organic innovation, and we, we look at M&A from time to time, you know, to make sure our product portfolio is complete. But in SD&A it's complete. I think one piece that was missing was structural analysis, which we just acquired BETA CAE.
That's right, that's right.
So I feel pretty good about the portfolio and, and go from there. And also, I think what is different... Okay, just one thing I want to comment is, what's different in 2018 to 2024, okay, I'm as excited about the SD&A as I was before-
Mm
... but what is different is the importance of EDA, our core business, is much higher-
Yes
... now than in 2018.
That's right.
So we want to make sure as we expand into SDA, which of course I launched all this six or seven years ago, but now the core business is more important because of AI and all this semiconductor is much more critical now in 2024 than 2018. So we want to make sure the R&D investment is well-balanced, and we focus on our core. Because without core, there is nothing. So that's why I'm more excited about the core investment in AI, you know, especially, you know, the Z3, X3 Palladium. You know, also, we are doing more investment in IP. IP should grow very well.
Yep.
So competitively, we are very well-positioned. Financially, I think we are very well-positioned, and we have a lot of support of, like, the big, what we call household customers. So we always talk about team, technology, and customers, focus on that. So I feel good about where Cadence is. And I think if you go back from 2018 to now, we are better positioned than we were six years ago-
Yeah
... even we are the first one to start all this. Yeah.
Well, Anirudh, great insights. Thank you for your participation today. Really appreciate it.
Yes, thank you. Thanks a lot.