Good morning. I'd like to welcome you all to Intel's Technology and Manufacturing Day. We're excited to have you here today. Most of you know this already, but Intel's Technology and Manufacturing organization is the lifeblood of this company, but it's also our most secretive. In fact, this has been the first time in three years that we've done a public briefing about our technology development and manufacturing. It's also important to note that this is the most in-depth under-the-hood briefing we've done on Intel manufacturing in my 17 years with the company. You want to be paying close attention throughout the day. We're going to have many technical disclosures and news items throughout the program. We will be posting information to Intel's newsroom in a couple of batches today, which will help you digest the information. Those will go live at 9:30 A.M. and at noon.
As well as after the event concludes, we will be posting the presentations to our newsroom and intc.com. Before I get into the agenda for today, I wanted to talk you through a few logistical details. First, please turn off the ringers on your phones. Second, we do have Wi-Fi networks. The registration information is on the back of your badge. With that out of the way, I'm going to touch on a few financial disclosure reminders before we get into the agenda. Today's presentations take place during Intel's quiet period before we announce our 2017 first quarter financial and operating results. While we will not be addressing first quarter information, presentations may contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially.
Please refer to our most recent earnings release, 10-Q and 10-K for more information on the specific risk factors that could cause actual results to differ. With that out of the way, we'll now move on to the agenda, and I'll just walk you through a quick overview on that before we get started. Stacy Smith, who leads our manufacturing operations and sales, is going to kick off the day. He'll set the stage for the subsequent technical discussions, and he'll cover our technology and manufacturing strategy and Moore's Law. He'll be followed by three of our top technologists from the Technology and Manufacturing Group. Mark, Ruth, and Kaizad will discuss Intel's Moore's Law leadership. They will reveal details about innovations we're delivering at 14 nanometers and 10 nanometers to enable significant density and cost per transistor benefits.
Mark Bohr is going to come back to the stage later this morning, and he'll kick off a portion of our agenda where we'll spend some time on Intel Custom Foundry. Today, you'll really get a sense of the foundry's role as a business serving both internal and external customers. He will discuss a new process being offered by the foundry called 22FFL, which stands for FinFET Low Power, and we expect it to have a range of IoT and mobile applications where power efficiency and fast time to market are critical. After Mark wraps up, we'll transition to have Murthy Renduchintala join us. He'll discuss our IDM model and our approach for co-optimized process, architecture, and IP innovation. He'll also address Intel Custom Foundry.
We'll wrap up the morning with an audience Q&A with Stacy, Murthy, and the General Managers of the Technology & Manufacturing Group, Sohail Ahmed and Ann Kelleher, who many of you may not have met before. We'll break for lunch, and partway through lunch, we'll start our final session of the day, a panel discussion about Intel Custom Foundry. Panelists will include executives from Arm, Cadence Design Systems, Synopsys, and Intel Custom Foundry. With that, we'll get the program started. Thank you for joining us today.
We don't stop for naysayers, complacency, competition, boundaries, or physics. Okay, maybe physics. Otherwise, there's no stopping us. Not when we put the silicon in Silicon Valley and changed the world. We make the rules. We made the law. We put everything under one roof, design and manufacturing. That's why our products are years ahead of everyone else. We're literally stacking atoms at 22 nanometers, 14, 10. We're pushing the boundaries of physics again with hyperscaling, bold new tech that blows past the litho barrier. Our pushing doesn't stop in the fab. We're making life better outside. Like this and this or that. We don't stop to wonder what amazing applications deep learning will bring because we're the ones bringing them. We don't daydream about autonomous cars because we're already driving toward it.
We won't ask about what new realities VR will unlock or the capabilities of a 5G network. We'll tell people how we unlock them. When it comes to the future, we're all for getting excited, but we prefer to get busy because at Intel, we're not fortune tellers, and we damn sure aren't spectators.
Please welcome to the stage Executive Vice President, Manufacturing, Operations and Sales, Stacy Smith.
Good morning, everybody. Welcome to our first ever Technology Manufacturing Day, where we are going to show you all the secrets of TMG. For those of you that don't know me, I'm Stacy Smith. I actually know a lot of you from my almost 10 years as Chief Financial Officer. As Laura said, now I run manufacturing operations and sales. Since I'm the Chief of Manufacturing Operations and Sales, that makes me CMOS. Come on. That kills in TMG. The sales part of my organization totally doesn't get it, but TMG loves that. Our ability to advance Moore's Law, to make products less expensive and more capable year in and year out is really our core competitive advantage. It's a huge driver of our business, and in truth, it's a huge driver of the worldwide economy.
It enables people to connect, it enables people to entertain themselves, to play and to learn. Moore's Law helps us solve some of the biggest problems on the planet, and it improves people's lives. I'm pleased to be here with you today. You're also going to hear from some of our top technologists and leaders. You're going to hear from Kaizad Mistry, Ruth Brain, Mark Bohr, and Murthy Renduchintala. It's a great lineup that we have today. Some of the presentations will get into the details of our technology. For those of you that aren't technologists, bear with us on that, but there's some really important information that we want to disclose. I'm going to kick off today by answering just a few of the questions that we get, things like whether or not Moore's Law is dead. Do we still have technology leadership?
Spoiler alert on those, it isn't, and we do. I'm going to talk about how our scale has become a bigger and more valuable competitive advantage. One of the topics you're going to hear about today is that the naming convention around how people name process technology nodes, has kind of lost its tie to the actual process technology nodes. Mark's going to talk to you about a standardized methodology of measuring density in a process and how we want to have an objective standardized methodology to be able to articulate how Moore's Law is being advanced. In the lead up to that, Mark will share that with you. In the lead up to that, I'll show you some of the ideas that we toyed with, but ultimately discarded in terms of our process naming methodology.
First, we thought that we could compare to a virus because that's a standardized size. For the record, 14 nanometer is about one-seventh of a virus. Our crack team of PR professionals pointed out to me that in the computer industry, no one wants to be compared to a virus. We discarded that. We came up with a really good idea. The idea was to have a nano Mark, compare everything to Mark Bohr, as kind of the godfather of Moore's Law inside of Intel. If I did my math right, and Mark confirmed this for me earlier, 14 nanometer would be 11 nano Marks. Just to put it in perspective, some of the competitive processes coming to the marketplace this year would be significantly less than that, more like 15 nano Marks.
Mark Bohr pointed out, and Ruth Brain was helping in this, it's good to have technologists, that not only does your height change over your life, but your height changes over the course of a day. This was not the standardized metric that we wanted. It wasn't constant enough, so we had to let that idea go. You'll hear a lot more about a less fun but real way that we want to measure process technology when we get to Mark Bohr's presentation today. All right. Let me get busy here. I want to take a second and define Moore's Law for you. Just starting at the highest level here. Gordon Moore's observation back in 1965 was that the number of transistors per square millimeter was doubling approximately every two years. That simple observation has become the heartbeat of technology.
It means that the capability of devices that use semiconductors doubles every two years. It's what brings us technology from supercomputers to virtual reality to wearables. It's really the driver of the industry. At its core, Moore's Law is really an economic law. It says that by advancing semiconductor manufacturing capability at a regular cadence, we can bring down the cost of making semiconductors over time. Since it's a doubling every two years, the cumulative effect of Moore's Law has been enormous. It has literally changed the way we live our lives. To illustrate this in a fun way, we like to look at what would happen if other industries saw innovation at the rate of Moore's Law, a doubling of capabilities every two years that kind of starts at the same timeframe that Gordon Moore pinned his law.
Car mileage, if you applied the same metric to that, would be so efficient that you could go the equivalent of the distance between the U.S. and the Sun on a single gallon of gas. You could feed the entire planet on a single kilometer of agricultural land. Space travel would have gotten to the point that you could actually travel at 300 times the speed of light. Again, coming back to my new role of Manufacturing, Operations & Sales, I have found that the key to the hearts and minds of our technologists is to show a picture of the Starship Enterprise in a presentation. I'm going to do that all the time. All right. Let's shift gears now to directly answer one of the key questions that we get from you from time to time, which is whether or not Moore's Law is dead.
By the way, I was in the factories in 1990. We were talking about this out in the foyer. That was about the time that we were progressing lithography to the point that the lines that we were scribing on the wafer were more narrow than the wavelength of light. As we led up to that was seen as this insurmountable technology wall, that there was no way that we were going to be able to get through. It wasn't even a blip on the Moore's Law cadence. The reality is that we're always looking out five years. We have good insight into how we solve the problems in the next five years. You're going to hear a lot of that today. We do a lot of pathfinding for the five years behind that.
Always when it's 10 years out, it's the view that we're not going to be able to solve the problems that exist. As we get there, we do solve those problems. The short answer, as you look at this chart, is that Moore's Law is not dead. At least it's not for us. These are our curves. Let me take a second and walk you through the charts behind me, which shows that for Intel, Moore's Law is alive and well. Starting on the left-hand side, what that curve shows is how scaling or density is improving over time. This is a log scale, and it shows how much we can shrink the transistors every generation. This is what drives Moore's Law for us. The transistors shrink so that we can double the number of transistors at every node.
The fact that those dots for 10 nanometer and seven nanometer are below the historical line is actually quite significant. You'll find that when the technologists in TMG draw dots, they don't do that loosely. What it says is, that we are getting a greater than normal density benefit for those processes. That's an important point, and I'm going to come back to that in a minute. The middle graph shows that the cost per square inch of technology goes up. It just gets more expensive to make the wafer. That's not a surprise. That's been a constant in our industry, and you'll hear more about that from Mark. The way that these curves come together is that every generation, that cost per square millimeter to manufacture a wafer goes up, but we shrink the transistors.
At the end, we get a decline in cost per transistor. You can see all of that come together in the chart on the right. Our cost per transistor is coming down at a slightly better rate than the historical trend. That says that for us, Moore's Law is alive and well. We get to decide what to do with that benefit, that benefit of a shrinking or a declining cost per transistor. We can either keep the die size constant and add performance capabilities and features, or we can decide to shrink the die and reduce the cost of each product. The reality for us at Intel is we do both because of the breadth of our products. In some cases, we take that benefit as a smaller die size, so lower cost products to go after new markets.
In other cases, we go after more and more performance and features because we get sell up and we can enable new usage models. The benefit of Moore's Law is that we can do all of that. We can improve performance, we can add features, and we can reduce costs. In a little while, I'm going to show you some of our actual cost data so that you can see the impact that these Moore's Law declining transistors curves has on reducing our costs. Over the course of the rest of the morning behind me, you're going to get a lot of insight into the actual technologies that we're using to continue to enable this. The chart on the previous page showed cost per transistor coming down from process to process. We know that the time between processes, the time between nodes, has gotten longer.
It's gotten longer for us, and it's gotten longer for the rest of the industry. Given that, you might wonder whether or not we're getting the same annual benefit to Moore's Law. We're showing that we're still coming down node to node, process to process, but as that time gets longer, do we still get the same annual benefit? The short answer to that question is yes, and I'll show you a little bit more about this in a second. We're getting the same year-on-year improvement, even with that longer time as we go from 22 nanometer to 14 nanometer, from 14 nanometer to 10 nanometer. It goes back to that density curve that I showed you a couple of slides ago. We're getting a larger than normal density benefit as we go from 14 nanometer and as we go to 10 nanometer.
In essence, we're taking bigger steps generation to generation, which is enabling us to stay on the historical trend. We're able to do that because of a strategy called hyperscaling. There are several underlying technologies that enable this, but there's a really important one called self-aligned double patterning and self-aligned quad patterning. You're going to hear about that in Ruth's and Kaizad's presentations. It gets a little technical, so I'll give you a spoiler alert for the non-technical people in the room. All you need to know is it's really, really cool, and we're very lucky that these people work for us. It's taking us longer to go from node to node. When Gordon penned Moore's Law, the time between nodes at that time was more like 18 months. Over the course of my career, that became two years.
Now it's more like three years to go from node to node. We're able to take bigger steps in terms of density improvement, and this is what's enabling us and allowing us to stay on that same improvement rate that we've achieved in the past. In addition, we're taking advantage of the longer life at each process node to introduce process optimizations. We have a really clever naming convention for these. We call them 14 nanometer plus, 14 nanometer plus plus, likely be 10 nanometer plus, 10 nanometer plus plus. Be easy for all of us to remember. Those optimizations allow us to bundle together process technology improvements, architectural innovations, new IP blocks to enable an annual cadence of products to hit the market every year. Murthy is going to talk a lot about that in his presentation.
The key for us is an annual improvement so that we can deliver to the customers something new and fresh and enable new usage models for them. This chart shows the impact of hyperscaling that I was just talking about. If you look at the 14 nanometer and the 10 nanometer chips that are to the right, what you see is that shaded dotted line shows what the die size would be. This is a feature constant view of the world, and we know that sometimes we invest Moore's Law in more features, and I'll come to that in a minute. A feature constant view of the world, and the shaded area shows what those die sizes would have been if we were just on the traditional Moore's Law scaling, which, by the way, is really good scaling. With hyperscaling, we're getting that bigger benefit.
You can see the impact on this chart. By the time you get to 10 nanometer, because of the cumulative effect of the steps that we're taking at 14 nanometer and at 10 nanometer, we get about half of the die size at 10 nanometer that we would have gotten with normal scaling. That's, again, assuming that we apply all of the benefit to die size. As a recently reformed CFO, I do feel compelled to show you a couple of actual cost curves. I think this really illustrates, at the heart, how Moore's Law works in practice within Intel. These are the actual cost curves for us for 22 nanometer and 14 nanometer product families. The first product on a process, as you would expect, is a relatively expensive product, right?
You're coming onto a process when the factory is ramping and when yields are a little bit lower. The second product typically comes in at the sweet spot of costs and then carries on to hit the optimal cost. On the left of this chart, you see the 22 nanometer product family. That's Ivy Bridge and Haswell. As you might recall, Haswell on 22 nanometer was one of our company's lowest cost products ever on one of our highest yielding process technologies ever. On the right-hand side, you see our 14 nanometer product families, and for the first time here, you see that plus and plus plus going on here. They follow that similar trend as we go from Broadwell, which was the first product on 14 nanometer, to Skylake, and then to Kaby Lake.
You see here that Skylake, by the point that it's ramped, gets to a similar cost to Haswell at the same time in its life. You see something really interesting with Kaby Lake. If you take out your ruler, and I know some of the financial analysts in the back will, you know who you are, you're going to see that Kaby Lake at launch is actually a little bit lower than Haswell was. We're getting a great cost in 14 nanometer as we get to those later waves of product. That actually shouldn't be a surprise. I think you've seen this kind of information from Intel in the past. There's something that's really important here. Kaby Lake has 800 million more transistors than does Haswell. It scores 30% higher on common metrics like 3DMark.
Kaby Lake enables entirely new usage models like immersive virtual reality and those kinds of things. It's an entirely different kind of product, entirely different class of product, frankly. The truth of us, of Moore's Law, resides in those cost curves. We can bring new capabilities to the market at a similar cost to the generation that came before it. The prior graph showed actual product costs, but that can be impacted by things other than Moore's Law. If you think about it, as we progress our product line from 2 cores to 4 cores, the die size can increase and our unit costs presumably go up in that model. It can be impacted by mix. Presumably, we get paid for that, but still, that cost trend is impacted by that mix. This graph is an all-in cost for our PC CPU product.
It just isolates that segment of the business, and it shows our actual curves of what we've achieved in terms of cost per transistor since 2004. This is an all-in actual cost for the company, for the PC client business. It's cost per million transistors, if you think about it like that. It's kind of the corollary to Moore's Law, where it's showing cost per million transistors as opposed to density. This is also on a log scale, and this is the first time that we've shown this data publicly. This chart is the realized benefit of Moore's Law to our cost structure over time. This is cost per million transistors, so it normalizes for mix. It's the entirety of our PC product business. You see something interesting here because we put the node transitions on here.
Even with that longer time between nodes, we're staying on the same realized cost per million transistor curve. This is the benefit of hyperscaling that I was just talking about and the intra-node optimizations. While I'm not showing 10 nanometer on this chart, I can say that based on everything that we know about 10 nanometer, we expect that this trend will continue out through the 10 nanometer generation. Remember, I told you earlier, there are two benefits to Moore's Law. One is that costs come down over time, which I just showed you, the other is that we can improve the capabilities of our products year in and year out. We can do more capable products for data center, for machine learning. We can do more capable products in the client space. We can go after new markets.
You can see in our financials over the last several years, the impact of having this Moore's Law leadership has impacted our financials, not just in the cost, but also in the competitiveness of our product line. The best way to view that is in viewing the gross margin of the company and how it's shifted upward. It's a combination of the cost that we've been achieving and the capability of our products over time. We continue to get the benefit from Moore's Law, as many of you have reported, there's confusion out there around how companies are naming node transitions. The question out there now is whether or not we still have a lead. Others are coming to market with 10 nanometer sometime this year. Let's hit that question head on.
This chart shows logic area scaling, which is a good way to compare process technologies between companies. If you look at the blue line, which is the Intel line, you can see that we're staying on the historical Moore's Law curve. In fact, at 14 nanometer, we're doing slightly better as a result of hyperscaling that I just talked about. When you look at the pink line or the red line, you see that for others, that trend line has flattened out. You really saw this start to happen as they brought in FinFET transistor structures into their process technology. They called those node transitions, but they actually weren't getting a density improvement as they were introducing that. That caused a flattening out of the curves.
You can see that since that point, they've really diverged pretty significantly and no longer match what we would traditionally call a node advancement. The result of this is that the technology that's coming to the market this year from others is equivalent in density, and you'll get more of that from Ruth today, to our 14 nanometer technology. For us, 14 nanometer is a technology that's been in production for three years. I just showed you those cost curves, and we've shipped on the order of half a billion units on 14 nanometer, and others will just be coming to market sometime later this year with it. It's apparent that the naming convention has caused some confusion in the marketplace. As a result, we're proposing that we, in conjunction with you, put some weight behind an objective measurement that measures process technology empirically and independently.
It's not quite as fun as nanomark, it probably makes more sense for the industry, and Mark Bohr will talk about that in his presentation. Now I'm going to switch gears a little bit and give you a sense of the scale of our worldwide manufacturing operations, which is one of our key competitive advantages. The investment required in this industry is enormous. It costs about $10 billion to build a single modern fab. You saw this play out a few months ago when we announced that we were going to equip Fab 42. That was a factory in Arizona where the shell has been built, and even there, just to equip an existing shell at seven nanometers on the order of $7 billion of investment. To just give you a sense of the scale of these projects, they're enormous.
When we built that Fab 42 shell, we had over 5,000 construction workers working on the factory. It's one of the largest construction projects on the planet. To put this investment into perspective, we've invested around $50 billion in CapEx over the last five years. I use the term invested here on purpose. This is one of our most valuable competitive advantages, and I believe that we get a really strong return on that investment by achieving product leadership and by being able to bring down our costs generation by generation. One way to measure this when you're looking at a capital-intensive business is in return on invested capital. Our ROIC over this five-year horizon has been slightly above 15%, which puts us in the top quartile of the S&P 500. Scale is more than just bragging rights for us.
To get a return on that $10 billion of investment, you need significant volume to be able to fill just one modern factory, not to mention being able to have a network of factories, which also is a competitive advantage that I'm going to talk about in a minute. You need to have a very significant skill set around technology development. The technologies that work on this stuff are solving some of the most difficult engineering problems on the planet. A decade ago, when you look at this chart, there were 18 companies that had their own leading-edge factory. Think about that. 10 years ago, 18 companies. Today, we're down to four. It's us, Samsung, TSMC, and GlobalFoundries. Of those four, there's only three of us that are really investing in developing our own process technology development at scale.
Of those, there's only two of us that are left as integrated device manufacturers. Murthy, in his presentation, is going to talk a lot about the benefit that he gets by being able to partner with the technologists in the manufacturing organization to optimize things for the needs of his product line. This is hard stuff. You need scale and you need skill, but I'm convinced there's an increasing competitive advantage that's going to accrue to those few players that can do this well. We have global scale, and we don't just invest in one factory, we have multiple factories. We have leading-edge factories in the U.S., so in Arizona and Oregon, in Ireland, and in Israel. We have a trailing edge factory in New Mexico.
In addition, we're building our first wholly owned memory factory in Dalian, China, that's starting off on 3D NAND, and over time, we'll transition to 3D XPoint. In the leading-edge factories, we employ a very strict methodology called Copy Exactly! This lets us ramp those factories fast and get to the world's highest yields for the complex devices that we do. It also gives us a model where we have fungible capacity to respond to changes in demand, and that becomes really important as we think about our supply chain and how quickly the demands of the marketplace can change.
There's another element to this ability to respond to changes, and that's that we have a methodology where we build in forward reuse of our equipment, so we can roll forward a lot of the equipment from one generation to the next. We build our factories such that we have several generations of future technology that we can put in those factories. That gives us the ability to respond to changes in the marketplace, and it gives us the ability to ramp in place without having to build new factories as we go from process technology to process technology. We only have to build factories when the demand grows or when our business grows to the point that it dictates the building of a new factory. In addition to our fab capacity, we have assembly test sites in Malaysia, China, and Vietnam.
We also do a reasonable amount of outsourced assembly tests, so we have some good sense of what the costs are out there. One thing I'll say about our assembly test capability is that we do achieve world-class costs internally in terms of our assembly test factories. Even more important, increasingly, packaging technology, assembly test, and some of the associated technologies that come out of that are becoming a really important differentiated capability that gives real value to our customers. Mark and Murthy will talk about something called Embedded Multi-Die Interconnect Bridge, or EMIB for short. It's actually game-changing in the way that it allows us to put together different IP blocks into a product that can come from different process technologies and do that in a way where you get super high performance.
To give you a sense of the numbers involved in our technology and manufacturing organization, we have more than 30,000 people that are working in the Technology & Manufacturing Group associated with those six fabs and three assembly test sites and the associated technology development that goes into them. We have over 4 million sq ft of manufacturing clean room space, and we ramp these factories at a blistering pace to a really unprecedented volume. As a data point, we produce over 10 billion transistors a second out of our fab network. We also have a very substantial footprint in the U.S., by far the largest footprint of any semiconductor company in the U.S. Of the high-tech manufacturing jobs that I talked about on the prior page, more than half of those employees are based in the U.S.
In contrast, 80% of our revenue comes from products that are exported to countries outside the U.S. We're one of those rare companies that does most of our manufacturing in the U.S. to service markets that are mostly outside the U.S. In total within the U.S., here I'm going a little bit more broad than just manufacturing. I'm looking at all of our R&D. We have over 50,000 high-tech workers, and over the last five years in the U.S., we've been the largest capital investor in the technology space as we've built and equipped the factories here in the U.S. In addition to the jobs created, we have a very substantial impact on the U.S. economy. Our contribution to the U.S. GDP was recently sized at around $90 billion. It's enormous.
It takes a finely tuned supply chain to manage this complexity. We have one of the best in the world. We get wonderful costs as a result of our scale, even more importantly, we've developed the capabilities to work really closely with our customers to embed in their supply chains to then help them through transitions to delight them as we introduce new products and bring technology to the market. To put this in perspective, last year, $10 billion of our revenue over the course of the year came from products that didn't exist on January 1st. It just shows how fast our product line transitions. We have to have the supply chain that allows us to adjust to those levels of changes.
More importantly, we have to be able to work with thousands of customers all around the world to help them through the transitions, to get the right inventory in place, to help them with the design work, to make sure that they can respond to the new products that we're bringing to the marketplace and ramp those in the market to deliver ultimate value to the consumers. This is very important to us, it's very important to them. I think it's become an increasing competitive advantage for us as the world has consolidated and gotten more complicated. I'm going to switch gears here. I'm going to talk about our foundry business. First, let me show you some data on the addressable market. In 2016, the foundry TAM was over $50 billion.
If you look at the leading edge portion of that market, which is the orange bar at the bottom, it's just under half of the overall TAM. Here we define leading edge as 28 nanometer and below, which would be consistent with how the foundry providers define the leading edge. Getting back to the is Moore's Law is dead question, one of the questions I sometimes get is whether SoCs need the kind of leading-edge capability that we provide. When you look at the driver of that orange bar there, why it's been growing so fast, really the dominant driver of that growth has been high-end mobile SoCs that's driving the build-out of that capacity. Those customers are valuing the performance and the energy efficiency that they get by being on more advanced technology. One last data point on this chart.
When you look at that orange portion, the bottom part, the leading-edge portion of the market, there's one company that has about 70% share in that market. The characteristics of this market is that it's a big TAM, it's growing fast, and the people that we're working with want choice and innovation in the marketplace. Let me just dissect a little bit the $23 billion portion of that orange bar. What you see is about half of it is on 28 nanometer, and the remainder is on the more advanced nodes. This portion of the market has been growing fast, as I said. It's been growing at about a 14% CAGR between 2010 and 2016.
The key for us in this space, this has been a journey for us, has been to develop our capabilities so that we can address what customers want, so that we can move in our journey from being really very much a custom partner to having more general purpose capabilities to work with a much broader set of customers. You can see this journey that we've been on, it's really accelerated over the last six months. As we focused on building out our capabilities, the first place that we focused was in bringing our silicon capabilities to this market. We've made FinFET transistors, High-K Metal Gate, strained silicon, all available to our customers. Second, we've been investing to develop a differentiated collection of leadership IP that we're making available to customers, and that ranges from Intel architecture cores in some cases, FPGAs, optical high-performance SerDes.
We're bringing some of our leading interconnect capabilities, like EMIB that I talked about, to this market, again, in order to create value for the customers that work with us. Third, we're now working very broadly with ecosystem tool, EDA, and IP providers to build a robust ecosystem around our foundry. Bottom line, we're trying to provide the technologies, the tools, and the services to make it easy and compelling for customers to design on us and to work with us. We now have the capability to go in and do customer co-optimization on a pretty regular basis, and we've done dozens of those. To give you more insight into this afternoon, there's going to be a panel on our foundry business, as Laura said, that includes some key partners, as well as the GMs of that business. Our current foundry offerings.
Our first customers were on 22 nanometer, that was primarily for the networking market. At 14 nanometer, we're seeing interest from networking and mobile SoC customers. One example of this is at Mobile World Congress, we announced in conjunction with Spreadtrum that they're going to be using our 14 nanometer process for mobile SoCs. On 14 nanometer, we also won a very large FPGA customer that it turned out we liked each other's technology so well that we ended up buying them. Now we're deep into the design work on 10 nanometer products. The customers who are interested in this process span from the performance segment of both the client and the mobile markets. If you think about it, our current offerings target about half of the leading-edge portion of that foundry TAM, the left-hand side of that foundry TAM.
Today, I'm really excited to announce, for the first time publicly, a process is targeted at delivering high performance and also ultra-low power. 22 nanometer FinFET Low Power, herein forever now more known as 22FFL. This platform blends high-performance capability with ultra-low leakage that enables our customers to do extreme integration, where they need both performance and low leakage on the same product. A few characteristics of 22FFL, by the way, Mark will talk about this in more detail. 22FFL can do high performance, the key change for us is that it can also do that ultra-low leakage. To put it in perspective, we're seeing more than 100x lower leakage than leading planar processes, 100x improvement, with much less complexity.
This allows us to provide that extreme integration capability to our customers, where they can put performance IP and low power IP on the same product, they can do it with a much lower cost of design. They can get to market fast, they can get designs to the market fairly easily. It's the easiest to use FinFET process in the industry. To put this in perspective, for some of our internal foundry customers, they've been able to bring out products in less than half the time with less than half the cost. Lastly, 22FFL supports full RF integration, because it's built on our high-yielding 22 nanometer process, it's cost competitive with 28 nanometer planar technologies. Think of this as 22FFL as FinFET for the masses, it gives us a leadership process to go after the other half of that leading-edge foundry TAM.
I'd like to recap some of the things that you've heard from us today and that you're going to hear more about over the course of the rest of the morning. First off, Moore's Law is alive and well. We have a three-year lead, 14 nanometer, over the rest of the industry. The industry is consolidating, our scale is both unique and a growing competitive advantage. Very importantly, we're making the investments and growing our capabilities to build a foundry franchise. Before I go, I have just one more thing that's important to the company and that I want to share. One of the reasons that I joined Intel so long ago was that I had a sense that the people here wanted to make a positive impact on the world. Clearly, we do that through our products.
It's one of the ways we make a positive impact on the world because we let people solve important problems and to connect with each other. We also try to be good stewards of the planet. I have to say, I'm so proud of what this organization has done and how they conduct their business. One example, over seven years ago, we started a journey to establish a responsible supply chain for conflict minerals, and we were one of the first companies that was able to validate our products as conflict-free. We're the largest voluntary corporate purchaser of green power in the U.S., and we've been number 1 on the U.S. EPA list for nine consecutive years. As of last year, we're now also the largest purchaser of green energy in Ireland.
We're deep into the work to ensure that the human rights of the people who work in the supply chain are ensured. We don't do this for the recognition, but we are recognized for our work here. We're ranked as one of the world's most ethical companies by both Forbes and Ethisphere. We're number 1 on the EPA's national top 100 companies list, and we're in the Dow Jones top sustainability index. Bottom line, we're trying to do good as we do well. This is something that's important to Brian, it's important to me, it's important to our board. More importantly, it's important to the employees of the company. It has an impact. It's one of the things that allows us to hire the best and the brightest and put them to work solving some of these tough engineering problems, all the while making a positive impact.
With that message, I'm going to turn it over to some of these smart and committed people to carry on the presentation from here. Thank you very much.
Please welcome Intel Senior Fellow, Technology and Manufacturing Group, Director, Process, Architecture, and Integration, Mark Bohr.
Good morning. Today, I get to talk to you about my favorite topic, Moore's Law leadership. Before I do that, let me say that last night during our dry run, Stacy Smith surprised me with his new density metric, nanomarks. Trust me, I have a more serious proposal later in my presentation. Let me start with my key messages. First, Intel leads the industry in introducing innovations that enable scaling. Hyperscaling on 14 nanometer and 10 nanometer provide better than normal scaling while continuing to reduce the cost per transistor. Intel's 14 nanometer technology has about a 3-year lead over other 10 nanometer technologies with similar logic transistor density. Intel's 10 nanometer technology provides industry-leading transistor density using a quantitative density metric. Enhanced versions of 14 nanometer and 10 nanometer provide improved transistor performance and extend the life of these technologies.
Finally, the overall message, Moore's Law is alive and well at Intel. Here I show a timeline for when Intel introduced our major technology nodes going back to 90 nanometers in 2003 up to our 10 nanometer technology coming out later this year, and also show when others introduced their various technology nodes. It was back on the 90 nanometer generation for Intel, that's 2003, when we were the first company to introduce strained silicon transistors in production. For those of you who can remember back to that time, other companies were exploring a biaxial version of strain. Biaxial strain never worked, never went into production. Intel invented a unique uniaxial strain technique that everybody copied about 3 and a half years later. In 2007, on our 45 nanometer technology, we were the first company to introduce and produce High-K Metal Gate transistors.
Again, if you remember back to that period of time, other companies were pursuing a gate-first process flow. Intel introduced a gate-last or a replacement metal gate process flow, and eventually everybody copied our gate-last flow, and it was at least 3 years later. On our 32 nanometer technology, we were the first company to develop a self-aligned via process flow for our interconnects that allows interconnect pitch to scale better than in the past. Again, it was more than 3 years later before other companies in our industry copied that approach. We are the first company to go into volume manufacturing with FinFET transistors. Of course, we called them Tri-Gate at the time, but we now call them FinFETs, and it was more than 3 years later before other companies first started producing their FinFET technologies.
On our 14 nanometer technology, which started volume production early in 2014, we started to use hyperscaling to deliver better than normal scaling techniques. Ruth Brain, in her presentation that follows mine, will describe in more detail what those hyperscaling techniques were on our 14 nanometer technology. We expect to see similar techniques on other 10 nanometer technologies coming out sometime later this year. Finally, later this year, we are coming out with our 10 nanometer technology that introduces some other forms of hyperscaling. I think it's fair to say that Intel has developed all of the major logic process innovations used by our industry over the past 15 years. We've received industry recognitions to reflect this. In 2008, we received the SEMI Award for our strain-enhanced transistors. In 2012, we received the SEMI Award for our High-K Metal Gate transistors.
In 2015, another SEMI Award for first implementation of FinFET transistors. Last year, we won the prestigious IEEE Corporate Innovation Award for our pioneering work on High-K Metal Gate and Tri-Gate or FinFET technologies. Let me talk about logic area scaling. This is a type of graph you've seen before, logic area on the vertical scale, in this case relative to our 45nm technology from back in 2007. We achieved, using this metric on the right, the simple gate pitch times logic cell height metric, we achieved about a 0.49x area reduction on our 32nm technology. Did a little bit better than that on our subsequent 22nm technology with about a 0.45x logic area scaling. This is a pretty easy metric to use to measure on our wafers and on any other company's wafers.
I think it's time to change that, to look beyond that metric. This gate pitch times cell height metric is deficient in two key ways. Number one, it's not a very comprehensive transistor density metric. There are some important second order design rules that affect the area, the size of logic cells, not comprehended just by logic cell height and transistor gate pitch. The other problem with this metric is that it's a maybe fairly good relative metric. You can say using this metric, process A appears to be denser than process B, but it doesn't give you a hard number that you can really compare technologies both in the past and some of the latest technologies. I think it's time to move beyond this metric. The metric we propose is not a new metric.
It's a metric that's been used by other companies in the past and seems to have been forgotten or ignored. This is a metric that measures the area and the transistor density in two very common logic cells. On the left-hand side is a 2-input NAND cell. Of course, I'm not referring to NAND memories in this case. I'm talking about a logic cell that performs a NAND logical function. It has four transistors and is a fairly small logic cell, but very common in any logic circuit. On the right is another logic cell, maybe on the other end of the spectrum of complexity and density. That's a scan flip-flop logic cell. Whereas the NAND cell on the left has two active gate pitches to determine its width, a scan flip-flop cell usually uses somewhere between 20 and 25 active transistor gates.
It's obviously a much larger cell, many more transistors, and sometimes slightly different transistor density than the NAND cell on the left. What they do share in common is they have the same cell height, but the cell width will depend upon whether it's the simple cell or the complex cell. Of course, any logic circuit uses a wide range, a wide variety of logic cells in between these two extremes, but these two kind of cover the range. The metric that's used in the past, and I propose we resurrect and start using again, is this NAND plus scan flip-flop metric, where what you do is you, again, calculate the transistor density in the NAND cell, then you calculate the transistor density in the scan flip-flop cell, apply weighting factors that historically have been a 0.6x for the NAND, 0.4x for the scan flip-flop.
Go through that simple math, you come up with a number of transistors per square millimeter. When I apply that metric to Intel technologies, I come up with this trend. Again, now the goal is ever higher transistors per square millimeter, ever higher density. It will be an upward-sloping curve as opposed to the area curve, which is a downward-sloping curve. Using this metric, our 32 nanometer technology provided about a 2.3x increase in transistor density, about a 2.1x increase on our 22 nanometer technology. Our 14 nanometer technology that Ruth will talk more about after my presentation delivered a much bigger gain using hyperscaling to deliver about a 2.5x increase in transistor density.
Our 10 nanometer technology that Kaizad will talk about later this morning, it provided an even bigger jump, again, with the use of the unique hyperscaling techniques used on our 10 nanometer technology, an increase of 2.7x in transistor density. These are big steps. Our 14 nanometer technology and our 10 nanometer technology are bigger than normal steps, providing 2.5 and 2.7x increases in transistor density. Yes, they've taken longer, we've taken bigger steps, we've taken a little bit longer, we're still on the historic trend rate of roughly doubling transistor density every two years. Moore's Law is alive and well at Intel. My claim is that any company developing a logic technology should now be willing to quote not only whatever node name they choose for that technology, but a quantitative transistor density number.
In the case of Intel, our 14 nanometer technology delivers 37.5 mega transistors per square millimeter. Our 10 nanometer technology provides a little bit over 100 mega transistors per square millimeter. Now using measured data from other companies, here's a comparison of our transistor density rate of improvement versus theirs. As you can see, they're on a slightly slower slope. This, again, this is a quantitative metric measured using the NAND plus scan flip-flop metric. I'll point out that in recent years, their rate of improvement has been a lot slower than Intel on their 20 nanometer, 16 nanometer, and 14 nanometer technologies. If you compare their transistor density to our 14 nanometer transistor density, ours is about 30% higher, or 1.3x higher.
I think we can say. Here I've added a point, an open circle for the 10 nanometer technologies for these other companies. There have been various reports in the press that, yes, they are or maybe are starting production on these technologies, no product has yet to hit the marketplace. You can't actually find one of these chips to reverse engineer it. We don't know exactly when they have or will start volume production. We don't know exactly what the density of their 10 nanometer technologies are. Based on their public statements, it's somewhere around where I've put that large red circle. Their density is expected to be similar to our 14 nanometer technology, about three years later. Again, as I said earlier, any company that develops a logic transistor technology, they can give it whatever node name they want.
I think we all agree that node names have lost a lot of their meaning lately. They should also be willing to follow it with a quantitative transistor density metric. As I stated earlier, Intel's 10-nanometer technology delivers about 100 mega transistors per square millimeter. We expect these other technologies to be in the range of around 50 mega transistors per square millimeter, a full generation behind. All right. Let me remind you what Moore's Law is. It's not a law of physics. It's a law of economics. By scaling transistors, you can deliver lower cost per transistor, or you can take those lower-cost transistors and add more transistors to a product to provide more functionality, higher performance. Again, Moore's Law can deliver either more cost savings or more performance or some combination of the two.
Historically, microprocessor die area scaling has been around 0.62x per generation, more than the transistor density improvements that I showed earlier because a microprocessor is a mixture of several different types of circuits. There are, of course, the logic circuits, which tend to scale the best, but there are also I/O circuits and SRAM circuits and maybe some other analog circuits that typically don't scale as well as logic circuits. That's where the 0.62x number has come from. Note, if we had kept following this normal scaling path, and had started with a 100 square millimeter die on the far left, our 10-nanometer die size would be just a little bit less than 15 square millimeters. With hyperscaling used on 14-nanometer and 10-nanometer, we in reality achieved much better than that 0.62x area scaling factor for a feature-neutral die.
We're not adding transistors in this case. The 10-nanometer die would be around 7.6 square millimeters or about half of what it had been if we had stuck with normal scaling patterns. What does this mean for cost per transistor? I show three graphs here, starting with area per transistor on the left. If we had followed the normal 0.62x trend, we would be delivering those open yellow circles at 14, 10, and 7 nanometers. Those are hypothetical points. That's not what we're doing. The middle graph, there still would be a wafer cost increase to deliver that scaling. Maybe a little bit less than with hyperscaling, but still would have been a wafer cost or cost per area increase on those generations. The result in terms of cost per transistor is the graph on the right.
We would be deviating from the historic reduction rate, delivering a not so good cost per transistor. Maybe better than the previous generation, but a curve that would be flattening out. Here's one more hypothetical scenario to describe to you. Again, starting on the left, I'm assuming a normal area scaling, 0.62x per generation. That's a hypothetical for 14, 10, and 7. In the middle graph, we could have introduced a wafer size conversion from 300 millimeters to 450 millimeters. Of course, wafer size conversions deliver lower cost per area. That would really benefit 14, 10, and 7, and be a one-time reduction in cost per area on 14. That benefit still applies as you scale forward to 10 and 7. The result of that is the graph on the right.
A little bit better CPT improvement than on the original set of slides I showed, and closer to the historic trend rate for reducing cost per transistor. Here's what we actually did on 14 and now on 10 nanometers. Use of hyperscaling on 14 and 10 on the left-hand graph shows a much better than normal area scaling. On the middle graph, you have wafer cost is still going up, maybe at a slightly faster rate. The result in terms of the cost per transistor is shown on that right-hand graph below the trend line for 14 nanometers and certainly for 10 nanometers. Even seven nanometers will come in below that long-term trend line. I've talked quite a bit so far about area scaling, density improvements, cost per transistor.
Another important benefit of scaling and of Moore's Law is improved transistor performance and lower transistor power. The graph on the left shows Intel's trend for delivering improved transistor performance over different generations. The graph on the right shows our trend for reducing the dynamic capacitance of those transistors at the same time. Of course, capacitance affects active power, so you want a lower capacitance for lower active power. The quick message here is that Moore's Law, at least at Intel, continues to deliver higher performance and lower power. We're not standing still. We're developing performance enhancements on our technologies. On 14 nanometer, we first developed 14+ that delivers improved performance over the original version, and now also developing 14++ with an even bigger performance gain over the original technology. The performance enhancement is shown on the left-hand graph.
Notice on the right-hand graph that the dynamic capacitance is unchanged. The point there is that we are delivering increased performance without increasing dynamic capacitance and without increasing active power. Another point I want to make is that these changes and these improvements or enhancements in performance can be traded off for power. If you have a transistor that is inherently faster, then you can choose to operate that circuit at a lower voltage, and you give up some of that performance, but you gain in terms of a much lower active power. Now at the coming 10-nanometer technology, we also have in place plans for a 10-plus and a 10++ technology, delivering in each case improved performance while not sacrificing dynamic capacitance. In addition to developing those enhanced versions of the process technologies, we also develop a wide range of derivative technologies.
The table on the left just shows the range of device types, transistor types that we offer. We offer some devices for some products. Other products want a different set of devices, a combination of high-performance transistors, low-leakage transistors, analog and RF transistors, high-voltage transistors, high Q inductors, precision resistors, and capacitors. Those are the range of options that we develop for different types of products. We also offer different sets of interconnect stacks, low cost interconnect stack, high density interconnect stack, and maybe a high performance interconnect stack as well. Again, a range of process features, a range of process derivative technologies that we offer at each technology node.
Today, we have a wide range of products, some of which have been in volume manufacturing for a while on our 14-nanometer technology, on various derivative versions of our 14-nanometer technology, including a larger server and FPGA die and, of course, a smaller client and mobile die as well. Looking to our future, the use of heterogeneous integration options will become increasingly important. This is where you can not only combine maybe two similar die in a package, but in some cases, two very dissimilar die. Maybe you'll have a die developed on a technology optimized for high-performance computing, another die designed on a different technology optimized for communication circuits or for memory circuits or for many other purposes. I think heterogeneous integration will be a bigger part of our future. What are the options? What are the process options for implementing heterogeneous integration?
You can just use a standard multi-chip package as shown there on the top, but it has a couple of problems. Number 1, the package substrates have a relatively poor density of connections between the die above and the package below. Also, the interconnects or the traces in the package tend to have a pretty loose pitch, so the fairly poor density of the die-to-die connections through the package. Another option is the image in the middle, the use of a silicon interposer. You add another large silicon die as an interposer between the actual die up on top and the package substrate below. This approach provides good density for the connections between the die above and the interposer below. Also, good density of die-to-die connections through that silicon interposer.
It adds a higher cost because you have a pretty large silicon die below, and you have the added cost of through-silicon vias. The third option at the bottom is Intel's Embedded Multi-Die Interconnect Bridge technology or EMIB, as we call it for short. This technique inserts small silicon bridges inside the package, and when the die are connected to the package, some of the bumps are the normal loose pitch bumps that connect to the package, but other bumps around the perimeter of the die are a tighter pitch, and they connect to the tight pitch interconnects in that silicon bridge. The EMIB approach provides good density of the die-to-bridge connections, good density of die-to-die interconnects through that silicon bridge, and low cost because these silicon bridges are small and don't include the cost of any added through-silicon vias.
In summary, EMIB technology provides high density, high bandwidth, die-to-die interconnects. This is an increased view of the embedded bridge technology showing the package substrate below. You can see the thin silicon bridge embedded in the package, that has some relatively fine pitch interconnects that can provide the lateral connections from die to die. On top of them are two die, and they can be similar die, or they could be very different die for purposes other than computing. It can be for memory, it can be for communications. They have finer pitch bumps that connect to the embedded bridge below it. This is not just a process technology or a package technology innovation.
It's also a circuit design innovation because we have designed custom IO circuits on our die that are optimized for use with this embedded bridge technology, optimized for minimum die area, maximum performance, maximum bandwidth, and also low IO power. Just to show you some actual micrographs of the embedded bridge technology. Here I show in the middle an expanded view. You can see the silicon die on top. On the far right is one of those loose pitch bumps, the normal package bumps connecting to the package substrate below. In the middle, you see an array of many of the finer pitch bumps that connect directly to that silicon embedded bridge. Much higher density of bumps to the bridge with this embedded bridge technology. One more magnified SEM image. Here I show the actual interconnects they used on that embedded bridge.
Four layers of copper interconnects with certainly a much tighter pitch than you can do on any package technology, but also loose enough pitch such that they provide really good performance as they transmit signals from one die to the other. Again, our vision going forward is more and more heterogeneous products integrating different chips into a package optimized for their various purposes. Embedded bridge is a key technology that enables dense and cost-effective in-package heterogeneous integration. This is my last slide, so let me wrap up. These are the same key messages I started with. Intel leads the industry in introducing innovations that enable scaling. hyperscaling on Intel 14 nanometer and 10 nanometer provide better than normal scaling while continuing to reduce cost per transistor. Intel's 14 nanometer technology has about a 3-year lead over other 10 nanometer technologies with similar logic transistor density.
Our 10 nanometer technology provides industry-leading transistor density using a quantitative density metric. Enhanced versions of 14 nanometer and 10 nanometer provide improved performance and extend the life of these technologies. Again, the key message, Moore's Law is alive and well at Intel. Thank you for your attention.
Please welcome Intel Fellow, Technology and Manufacturing Group, Director, Interconnect, Technology, and Integration, Ruth Brain.
Good morning. It's wonderful to be here with you guys this morning. I'm hoping I can talk to you a little bit more about our 14 nanometer technology. My name's Ruth Brain. I'm with the Technology and Manufacturing Group in Portland, Oregon. I'm hoping today I can cover a few things. I'm going to talk more about Mark's density plots and really dive into the 14 nanometers in more detail. I'm going to talk about performance, I'm going to dive into some of the innovations that I'm really excited about, I hope I can convey some of that excitement to you about how we actually put together some of the self-aligned features that really make our interconnects capable of scaling. Let me dive right in with that. A few key messages.
I do want to go in through the Intel's 14 nanometer technology in more detail. We do have about a 1.3x density advantage than what you see in others' available 20/16/14 nanometer technologies. Intel's 14 nanometer technology is expected to be similar density to others' 10 nanometer technology, but 3 years ahead. Intel's 14 nanometer transistors have at least a 20% performance leadership compared to others' available technology. At the 14 nanometer node, Intel has really developed all these key enablers of hyperscaling, that really allow us to enable delivery of that cost per transistor benefit. I will spend some time on that, I hope I can convey a little bit of the physics there because it really is exciting what we're able to do. Let me start with just the density plots and go there first.
Let me go through some of the key features that enable our 14 nanometer scaling. If you look at what we do, we have to scale multiple types of different features to enable scaling. Fin pitch, interconnect pitch, the library cell height, as well as the gate pitch. We do aggressive scaling in all of these, different for different features, let me walk through those. At the fin pitch region on 14 nanometer, we did a 0.7x scaling down to a 42 nanometer fin pitch. At interconnects, we did a much more aggressive scaling of 0.65x down to 52 nanometers. Again, as I get further along in the presentation, I'm going to talk a little bit more about how we enable that aggressive pitch scaling.
For the cell height, we were able to use our high-performance fins to enable that cell height to reduce by more than 0.5x. For the gate pitch, we went from 90 to 70 nanometer gate pitch for a 0.78x shrink. That really, if you wrap it all up, I'm going to go through some of those details, you can see that we have an unprecedented 0.37x scaling for our logic area. Let me go through this graph in a little more detail to help understand it. This is an Intel graph relative to our own process. As Mark said, it's one good way for us to measure our own success. If you look at 45, 32, 22, and 14, you can see, if anything, we've been accelerating our rate of logic area scaling.
When we went from 22 to 14 nanometers, we took advantage of these new inventions in hyperscaling, and we were able to achieve 0.37x scaling. That really helped us with keep the cost per transistors and pointed out in a very aggressive area. I'm going to switch to the other metric because I do also want to put this in absolute terms that can really be measured and quantified versus the relative terms on the last page. If you look at logic transistor density using this metric that Mark walked through, 14 nanometer provides much better than normal logic transistor density improvement from an average of about 2.2 on prior technologies all the way up to 2.5x. That's over 37 million transistors per square millimeter, and there's a lot you can do with all those extra transistors.
If you look at what others' capability are and what they call their 20, 16, and 14 nanometer node, you can see we're approximately 1.3x better than those nodes as well. I'm going to go through some more of the details on that so people can really understand the various density metrics that go into this. Let me start with Intel's 14 nanometer technology and others' 20 nanometer technology that was introduced at a similar time. If you look at all the typical simple metrics that you can look at, gate pitch, logic cell height, fin pitch, and metal pitch that I already mentioned, you can see even on those simple metrics, Intel is ahead on every metric in terms of density. By in some cases, quite a bit.
The bottom line is what I really cut down to is this transistor density metric, where we're more than 30% more dense than anything that was available on what others call 20 nanometer technology. If you go ahead a year for things that were introduced a year after our 14 nanometer technology, as Mark pointed out, the rate of innovation was slower on some of those, and you can see incremental changes. 1 to 1.04 or 1.09. They did incremental benefits to those, but you can still see really world-class density on Intel's 14 nanometer. It's really at least 25% better when you actually go through those metrics. Even if you go through the basic metrics of just gate pitch, logic, cell height, you see the same answer. What we really like to get to is that very quantitative transistor density metric.
In even those cases, you see that there's a clear benefit. I also want to just reiterate, if you look at what's available with the way things are being named, the 14 nanometers is really expected to be similar density to others 10. If you look at the timeline, we've had 14 nanometer in production since 2014, which you can see from this graph. If you look at our 14 nanometers, and again, as Mark pointed out, there are not parts available today for us to really quantify. Based on available information, this is what we can see about the roadmap looking ahead. We expect they'll have similar density, but really, we do have a three-year lead. I think the number I heard was we have more than 450 million units out in production on 14 nanometer today.
We really have a lot of history doing that. Let me jump ahead to the performance, and I want to spend a little more time on 14-nanometer performance because we really also have dense performance leadership in this space, and it's important for our products to be able to offer that performance improvement. This is the same graph Mark showed, and then I want to walk into a little more detail on it. What we have done at Intel is we developed an initial technology, but we're still learning things. We're always enhancing that technology, and we're really formalizing that a little bit more by naming some of those enhancements to really enable product teams and others to take advantage of that so that we can really deliver world-class performance.
If you look at our 14-nanometer introduced in 2014, you can also see a 14+ technology introduced in 2015 and a 14++ in 2016. They offer improved performance without increasing capacitance or active power. As you said, depending on the product type we're looking at, we can trade those off, but this is sort of the basic curve with matched capacitance and what you can do for the performance. Let me go through a little more detail on that. One of the key advantages we have here is our knowledge of FinFETs. FinFET transistors were first introduced at Intel at our 22-nanometer node, and I show here a comparison on the left-hand side of a schematic of what those 22-nanometer FinFETs look like versus what they look like on 14, which is our second generation of it.
You can see as you compare the schematics in the two cases, we brought the fin pitches closer together, which I mentioned previously, so that we could get the improved logic density, and at the same time, we made them taller. That's what really allows us to continue to offer performance. Of course, making things taller and thinner is more challenging. It's like we're making a taller skyscraper every time. That's one of the key inventions that we've really worked out to be able to optimize for performance and density. As you can see on the right-hand side, these are actual images of our silicon wafers that I'm more excited about than just the schematic, showing really in production how much nicer those fins look.
As you go from 22-nanometers to 14-nanometers, because we have that learning and that underlying knowledge of how to make this work, we really were able to optimize them and produce better shapes and taller fins for that technology. Let me get into the actual performance data. I'm showing a couple of benchmarks of Intel's 14-nanometer performance. On the left-hand side of this is NMOS, and on the right-hand side is PMOS. I just marked down in the lower right-hand corner, that's where better would be. Then it would be lower leakage current at a higher drive current. Intel's 14-nanometer technology has a poly pitch. You see the 70PP. I mentioned we run the 70-nanometer poly pitch, and you can see what we ended up with performance. It was leading performance in 2015.
If you look at what we achieved in 2016, we continue to improve. We don't just stand still on these things. As you look at what we're able to achieve, we continue to create performance enhancements. A year later, we improved both NMOS and PMOS drive current by more than 12%. This is still at that same tight poly pitch. If you go into 2017, you can see we've added yet another device here. We've added an 84 poly pitch device for our highest performance segment. This really enables a 23%-24% drive current improvement in addition to our original 14-nanometer process. What we've offered here is the opportunity to have both density and performance.
If you take a look at what I can see as a comparison of what others are able to produce, and of course, I only look at what the best available of others is, this is where it looks like it's at. You can see even from best available, we have a 20%-23% performance improvement at the 14++ technology. If you wrap all of this up into a power versus performance set of curves, looking specifically at Intel, I've got our 14 nanometers shown in 2015, our 14+ in 2016, and 14++ in 2017. You can see that there's really a huge transistor improvement available so that we can enhance this on an annual cadence.
At a given power, you can choose to have 26% performance improvement, or you can choose to cut the power in half if you're willing to take lower performance. We can trade off along those curves to make it the best available choice for a given product. Let me also talk a little bit about the other capabilities that we offer, because we've talked a lot about the basic process and the FinFET transistors as well as the interconnects. I also want to point out that really our 14-nanometer technology offers a full range of features for product design needs. The schematic to the left here really shows kind of a cartoon cross-section of an interconnect stack with the silicon substrate at the bottom, transistors just above it, interconnects above that, MIM cap is a metal insulator metal capacitor that's available.
At the top, we have thick metal that we can use for inductors and other type features. We've added the capability to have high resistance substrates that are needed for certain product needs. We've also added the ability to have triple well or deep N-well type devices. We have low leakage and high voltage transistors available to us as well, which again are needed for certain applications. All of this is available in the silicon substrate. We've added RF transistors with both template and modeling for people that need RF capability. We've added precision resistors. Again, another key need if you need to accurately benchmark a certain resistance. Finally, when you get up to the top of the stack, you can see that we've added a high-density decoupling capacitor. This is this metal insulator metal layer that's at the very top of the stack.
It's a little bit hard to see in that cross-section. It's that thin layer with the via cutting through it, but that's a very high-density MIM stack. Finally, at the very top, we can add high-Q inductors with our TM1 capabilities. Really, if you look at the stack from the bottom to the top, we offer just a full range of capabilities for whatever the product needs are. This is part of our Intel IDM advantage in that we really work with our product teams to understand the basic need of the technology so that we can create that technology at Intel. I want to skip over my interconnect stack, which is one of my favorite portions of the stack. We offer a range there as well. We really try to have a mix-and-match set of stacks.
Circled in the sort of light yellow is our high-performance client stack. A high-performance client stack is really characterized by having tight pitches at the bottom and slowly transitioning to looser pitches at the top so that you can promote global routes that are routes that are RC limited. You can also switch to having this one I show in the green, which is a high-density SoC stack, where again, if you really need to optimize density, we can also take all these basic building blocks we put together and build them into the stacks that we want to create. Highlighted in blue is a feature that we can add or take out of the interconnect stack. For stacks that are particularly performance sensitive, we can add air gaps, which reduces the line-to-line capacitance to enable that.
Again, even in the interconnect stack, we have a range of capabilities that we can mix and match for the right product portfolio. Lastly, let me go through some of the key enablers for this, and this is really where I want to get into hyperscaling and some of the unique advantages of some of the things that we develop and invent at Intel. Innovation and really that ability to understand the physics and understand it so exquisitely that we can create things is what really helps us. That, to me, is one of the key drivers for what I love about working here. If you look at what we would call traditional scaling enablers, Mark already covered some of these, and I know they've been out in the market quite some time now, but let me at least mention them.
The High-K Metal Gate, the self-aligned via, and FinFET transistors. I think these are now familiar names to everybody in the industry because we put them together, and they really have enabled us to do our traditional scaling, and we've driven those breakthroughs. It's really exciting stuff. We have several generations of learning at this point on those enablers. What we've added at 14 nanometers, and we continue to add as we go to new process technologies, is new features and new inventions. The one I'm going to dive into a little bit on is the hyperscaling feature at 14 nanometers. Let me talk a little bit about interconnects. If you look at interconnects at 14 nanometers, we did an aggressive pitch scaling. We went from an 80-nanometer pitch on 22 to a 52 nanometer pitch at 14 nanometer.
We needed to invent a new technique to do that, and it's called self-aligned double patterning. It was first introduced into logic manufacturing by Intel, and it's really a key advantage to both density and yield. Let me explain a little bit more about that. If you look at what's available on the market, as many of you know, you can just buy 193 nanometer wavelength immersion single-pass tools. That typically allows you to print features that are down to around 80 nanometers. At 80 nanometers, you're using all sorts of enhancement techniques to create that, but that's what the capability looks like. To go beyond that, what you need to do is invent new patterning techniques. What we're going to talk about in the next few slides is a self-aligned double patterning technique, and I'll go through that detail.
Also, as Kaizad will speak about a self-aligned quad patterning technique. If you look at that range of what's capable, the standard immersion single pass could take you down to around 80 nanometers. Self-aligned double patterning can take me all the way down to 40 nanometers, and self-aligned quad patterning can take me down to 20. When you look at this, you don't see any gaps. I can now basically, if I've invented those techniques, I can choose where I want to be. That understanding really gets us to where we can make choices about exactly how we want to use our technology. In comparison, what I see out in the marketplace is you look at the, again, 193 immersion single pass, that's a commercially available tool. Everybody has access to that. Again, the capability is down to around 80 nanometers.
What others have done is just use a very simple technique where you do litho etch, litho etch. Now if you want to go below that, you need to do it three times. Litho etch, litho etch, litho etch. You can see you can just keep stringing those together. If you look at the comparison, what you can really see is you don't get the same pitch capability range as you do with these real inventions. They might be sort of very linear thinking about how you go from a previous technology to a current one, but it doesn't really enable you the breadth, and that's what that innovation gets us. Then let me point out one of the key things about it is that it's similar cost to these features, these capabilities that really can give us a bigger range.
If you look at self-aligned double patterning, I have a capability all the way down to a 40-nanometer pitch, and yet I've paid the same cost as LELE, which would only get me down to 60-something pitch range. That's really one of the key benefits of it. Let me dive into a little bit more detail on that self-aligned double patterning versus the LELE to try to help understand that. Here's just a picture of a double patterning, and to me, it's kind of like a baby picture and that you ought to see the beautiful baby on the double patterning, and I hope that's what you all see. There's a desired pattern to the left-hand side, and you can see that would be what we've drawn in a database. You can see how exactly that double patterning matches that image.
You can see how square the line ends are. You can see how beautiful and smooth the lines are along both dimensions. If you look at litho etch techniques, you can already see that these small feed-through features that are short, they're narrow, they're not as long as they need to be. They've got rounded ends. They really don't look like you'd want in a manufacturing process where you're controlling things down to the last nanometer. You can see in these images that it's really just not what you want. I want to just say here, you can see the clear benefits just from looking at images of these. Let me get through how you do that because there's other issues with just doing a litho etch technique versus the double patterning.
Let me start with self-aligned double patterning, let me dive into my excitement of how you actually create that because this is the good stuff. Self-aligned double patterning, you have to create a litho pattern on the wafer using resist. What we do then after that is we take and we do a thin-film deposition step that we call a spacer and basically wrap it over that, and that's what you can see in the blue. The beautiful thing about thin-film depositions is we can really control those down to the last nanometer. We really have monolayer film control over a lot of thin film depositions. We can deposit that over the litho stack with precision that's just exquisite.
What we do next is we etch the spacer, you can see in the next images, I've removed the spacer from the top of the resist as well as the bottom. I've spacerized, that's what we call in the industry, spacerizing the resist. I remove that photoresist, you can see I've cleaned it out, now I can just etch the trenches, I basically have nearly perfect control between the two sets of patterns I just created. If you compare that with litho etch, litho etch, that's what I want to show here side by side. When you want to do litho etch, that means you're doing it twice. You start with the first pass of litho, you etch those into the trench. You come back and do another litho pass.
If you have good placement and you're lucky, you basically get perfect alignment. That's my good placement view right here. You'd etch that second set of trenches, you'd end up with the same pattern. Both of these techniques, let's start by saying, will produce the same pattern. You're just not getting to them the same way. That's an if, because that's if you had good litho placement with that second pattern. Here's the other thing that can happen, which is that when you place that second pattern down, there's nothing that's really controlling that except for how good you are at placing it. You're trying to place something that is much, much smaller than a human hair with exact precision. All of a sudden, a litho placement of 10 nanometers, that's pretty darn good already.
You can see it's almost 10x looser placement than what I was able to achieve by going through that invention and putting down the spacer. When you go through the etch, you can see, well now it's offset. This picture really isn't that far out of scale for what you can end up with. You can now see that my two lines are way too close together for the one that was misregistered between them. Not only do I have a yield risk from this, I have a performance risk, because now if you look at the line-to-line capacitance, you can see the capacitance is different between these lines. For one set of lines, it's much less than they would've predicted in the modeling, and one, it's much more.
Now all of a sudden, product designs have to take that into account when they're creating anything, is that there's some random fab variation that they can't control. This is really one of the key risks with litho etch, litho etch. It has both yield and performance risk associated with misalignment between those patterns. To put kind of a fun point on it, this is the way I look at it very simplistically. When you do self-align, you're aligning a single mask to a single mask. You're the polar bear standing on the solid sheet of ice. If you look at litho etch, litho etch, for anybody that's a fab person, you're out there and you've got one foot on each piece of ice and you're trying to hold the ice together. I definitely want to be the polar bear standing on the one piece of ice.
The other one is the one that falls in the drink. There really is significant benefits you can see out of both the clarity of the image I showed, as well as the ability to just control the step as we go through the fab and make the manufacturing process work. Let me go into a little bit more about the 14 nanometer technology now in terms of what do we really deliver. Mark talked about this image, and he talked a little bit about the details of how we've changed the slope of the area scaling. I want to point out that not only at 14 nanometer did we just optimize this one metric. We also, if you look at our logic area, that's what we talked about in the logic area scaling. A microprocessor die has SRAM on it as well as I/O.
I show a scale factor for how they're scaled, as well as some weight factors here, which are typical of a client die. You can see that for SRAM and I/O as well, which are traditionally very hard to scale, we did very well here, resulting in a less than 0.5x area scale for everything. It's not that we're just picking one metric. We're really able, with these new techniques, to be able to do a full feature scaling. I want to just give an analogy for that. People get very excited about wafer size transitions. For the 14 nanometer hyperscaling that we developed, and because we were able to choose what pitch we wanted to do at a given cost, we were able to give 1.4x more units per dollar than traditional scaling.
That's roughly equivalent to either a 200 millimeter-300 millimeter wafer size transition or a 300 millimeter-450 millimeter wafer size transition. It's the equivalent. We got the benefit of a full node of scaling plus this extra. It really gave us a huge economic benefit, as well as allowing us to really pick and choose exactly how we wanted to land the process. In summary, I hope I've shed some light on our 14 nanometer technology. It's great stuff, it has to be. It's 1.3x denser than what we see in others' available technology. It's expected to be similar density to others' 10, but about three years ahead.
I did want to again hit the highlight of that performance advantage, both for FinFETs and our ability to control those and have second-generation, our ability to make them taller, our ability to choose interconnect pitches and control the interconnect stack. All of those really play into these performance advantages. Really, the thing that gets me most excited is that the 14 node, we really developed all these key innovation enablers to really enable where we wanted to be for both hyperscaling features and deliver those significant cost per transistor benefits. Thank you.
Thank you, Ruth. Before we disperse for the break, just a couple housekeeping items. We've got beverages outside. Stretch your legs, recaffeinate, use the time to do some informal mingling and Q&A with some of our speakers and manufacturing experts. With that out of the way, enjoy the break. We'll see you back here in 15 minutes. Thank you.
Please welcome Corporate Vice President, Technology and Manufacturing Group, Co-director, Logic Technology Development, Kaizad Mistry.
Good morning, everyone. Welcome back from the break. I'm excited to be here today to reveal to you for the first time some of the leadership features of Intel's 10 nanometer logic technology. This is our next step in logic technology evolution after the 14 nanometer technology that Ruth described for you a few moments ago. If there's one key message I want you to walk away with after you see my presentation, it is that all 10 nanometer technologies are not created equal. Shakespeare said, "What's in a name? A rose by any other name smells the same well." In this case, I think the great bard was mistaken, and I hope that once you've heard my talk, you will recognize that our rose smells sweeter. Here are the key messages that I'll be going through in this presentation.
First, Intel's 10 nanometer technology has the world's tightest transistor and metal pitches in the industry. In addition, I'll be describing to you some unique hyperscaling features, new innovations in our 10 nanometer technology that provide even greater density than the pitch scaling that we have. The result of those factors is that Intel's 10 nanometer technology will be a full generation ahead of what others call 10 nanometer. Next, I'll talk about enhanced versions of our 10 nanometer technology that provide improved power and performance within the 10 nanometer process technology family. Finally, I'll return to the theme of hyperscaling that Mark and Stacy introduced this morning, and really come back to that theme and explain again how hyperscaling allows Intel to continue the economic benefits of Moore's Law while swallowing the cost of these multi-pass patterning schemes that are needed to advance Moore's Law.
First, I'm going to talk about some of the key features of our 10 nanometer process technology. Of course, Moore's Law is built on scaling. Scaling means scaling pitches. It means packing wires closer together, packing transistors closer together, and in the modern era of FinFETs, it means packing fins closer together. In our 10 nanometer technology, we feature aggressive pitch scaling. The fin pitch is scaled from 42 nanometers to 34 nanometers. The minimum metal pitch is scaled from the 52 nanometers that Ruth described to 36 nanometers. This allows the cell height to scale by better than the traditional 0.7x. Our gate pitch is scaled to 54 nanometers. We feature aggressive pitch scaling, and for the first time in the industry, we use self-aligned quad patterning. I'll speak more about that in subsequent slides. We didn't stop with pitch scaling.
In our 10 nanometer technology, we have two additional innovations that add to the transistor density improvement. These are single dummy gate and contact over active gate. I will spend a few slides in subsequent material to go through those two unique new innovations. The combination of the aggressive pitch scaling and these new features delivers an unprecedented 2.7x transistor density improvement, significantly greater than the traditional Moore's Law cadence of 2x logic transistor density. If you look at the result of all these innovations, Intel's 10 nanometer technology provides a transistor density measured using the metric that Mark described earlier today of over 100 million transistors per millimeter squared for the first time in our industry's history. Intel introduced FinFETs for the first time in 2011 on our 22 nanometer technology. We were the first to do so.
With our 10 nanometer technology, we are now on our third generation of FinFET technology. With each successive generation, we've packed the fins closer together and made them taller. We pack them closer together to improve transistor density, and we make them taller to improve transistor performance. On our 10 nanometer technology, our fins are about 25% taller and 25% more closely spaced than the 14 nanometer technology generation. In fact, if you go and measure the fins, the fin pitch is 34 nanometers, and the fin height is about 53 nanometers in our 10 nanometer technology. You can see the exquisite fidelity of the patterning of these fins that allows us to extract the full performance and density advantage of FinFETs in our third implementation of this technology. The other key pitch for transistors is the gate pitch.
Intel's 10 nanometer technology features a 54 nanometer gate pitch scaled to be tighter than our 14 nanometer technology. If you compare that to the competition, Intel's 10 nanometer gate pitch is the tightest in the industry. We have traditionally had the tightest gate pitch in the industry, and we will continue to do so with our 10 nanometer process technology. That's the transistors, but you need wires to hook them up. This shows the minimum interconnect pitch trend for our recent technologies. Intel's 10 nanometer technology features a minimum interconnect pitch of 36 nanometers. We accomplished this with the world's first implementation of self-aligned quad patterning. Ruth went through the difference between self-aligned double patterning that we used on our 14 nanometer node compared to some of the other techniques such as litho etch, and she illuminated the advantages of the self-aligned approach.
We have taken that one step further in our 10 nanometer technology by introducing self-aligned quad patterning, meaning the original lithographic patterning is divided into four to have a pitch that is four times tighter than the original lithographic pattern. Using the same self-aligned techniques, we achieve exquisite control in terms of the placement of those lines and the fidelity with which the lines are patterned. If you compare that to the competition, we will have the tightest minimum metal pitch in the industry. Let me talk about some of the other innovations that give us the really phenomenal transistor density improvement that we have on our 10 nanometer technology. The first of these innovations is called contact over active gate. I'm going to spend a few minutes on this slide to explain to you what this innovation is and why it's important.
The picture on the left shows a traditional transistor with a gate contact. This is not quite a traditional transistor. It's a FinFET transistor, but for us, that's become normal. The gray lines are fins running from left to right, and the green line is the polysilicon gate running from top to bottom. Wherever the gate crosses a fin, that's a transistor. You have to make contacts to transistors. You have to contact the gate of the transistor to be able to turn the transistor on and off. For the last 30 or 40 or 50 years of the semiconductor industry, the gate contact has been made away from the active transistor. You can see it's below the active transistor, where the fins and the gates cross.
In our 10 nanometer technology, we allow the contact to be placed directly above the active transistor. This is a unique innovation that we are introducing in our 10 nanometer technology. There is a number of technology attributes and innovations that we need to introduce to allow the contact to be placed directly above the active transistor. You can see the advantage of this immediately. If you're trying to pack transistors closer together, you don't need that space in between the transistors where the contact used to be before. It's now placed directly above the transistor, and you can pack those transistors closer together.
We estimate that this contact over active gate technology, this revolutionary new feature that is a first in the semiconductor industry, allows for another 10% transistor density improvement or another 10% area scaling improvement over and above the pitch scaling that I described on the previous slides. We didn't stop there. We have another key innovation in our 10 nanometer technology called single dummy gate, and I'll spend a few minutes again on this slide to explain to you what it is, why it's important, and what it buys us. On the left is a 14 nanometer cell, the simple NAND cell that Mark talked about earlier. One thing you will notice is that at the edges of the cell, you have dummy gates, one on the left, one on the right.
In the middle, you see in green, the active gates that form the active transistors that are switching. On our 10 nanometer technology on the right, you see that we have what we call a single dummy gate, half on the left, half on the right. You can immediately see that this offers advantages for transistor density compared to the double dummy gate on the left. Now, some will ask, what's new about this? Well, it is true that others have offered single dummy gate in prior technologies, where the pitches were looser, and prior to the advent of FinFETs. Some of the difficulties with single dummy gate historically have been: How do you support single dummy gate on an advanced technology node that has FinFETs?
How do you match the transistor performance for transistors that are in the middle of the cell compared to those that are at the edge of the cell and close to those dummy gates? Those are not historically always matched, and that presents a modeling or circuit design challenge for the designer. Then finally, how do you do a single dummy gate on an advanced node with such a tight gate pitch as 54 nanometers? We have introduced unique innovations in our 10 nanometer technology to overcome those difficulties. We can support a single dummy gate where the performance of the center transistors and the edge transistors are closely matched. We're able to support single dummy gate on a FinFET-based technology with extremely tight gate pitches.
This is another key innovation in our 10 nanometer process technology that affords area scaling above and beyond the traditional pitch scaling. If you look at the metric that Mark Bohr proposed earlier of the two-input NAND cell and the scan flip-flop cell, which represents the broad array of logic cells that are used in a modern chip, you can see that the single dummy gate provides an effective additional 20% or more effective area scaling benefit compared to the double dummy gate that was used previously. It really is another key innovation that allows really aggressive area scaling on our 10 nanometer technology above and beyond the traditional pitch scaling. Next, I'm going to talk about the hyperscaling benefits of Intel's 10 nanometer technology, taking all of the features that I've just described and telling you what it means as a whole.
First, the fin pitch and metal pitch scaling allow the cell height to scale by better than 0.7x from our 14 nanometer technology. We scaled the gate pitch as well. The traditional pitch scaling affords an area scaling of about 0.5x, which is the traditional Moore's Law pace. If you combine all the pitch scaling elements that I talked about, including the world's first use of self-aligned quad patterning, we get an area scaling roughly consistent with historical Moore's Law pace of about 0.5x. We didn't stop there. We introduced these two additional features, contact over active gate and single dummy gate. The combined benefit of all of these innovations results in an area scaling of about 0.37x. This is the hyperscaling benefit of Intel's 10 nanometer technology, significantly faster than the traditional Moore's Law pace of roughly 0.5x area scaling.
If you look at that in historical context one more time, traditional Moore's Law scaling around 0.49x and on our 14 nanometer technology, again on our 10 nanometer technology, we use these unique hyperscaling innovations to provide better than normal 0.37x logic area scaling. If you translate that to the metric that Mark Bohr described earlier today, which is the transistor density, which continues to grow, we provide a 2.7x transistor density improvement over our already leading 14 nanometer technology. Really an unprecedented transistor density improvement in our 10 nanometer technology. Again, although it took us longer than two years to develop this 10 nanometer technology, we took a much bigger step.
If you look at that in historical perspective, you can see that our 10 nanometer technology, as was the case in our 14 nanometer technology, continues to keep Intel on the Moore's Law pace of roughly doubling transistor density every two years. We continue to maintain the rate of Moore's Law density scaling. If you compare us against the competition, you can see that with these unique hyperscaling features, the world's first self-aligned quad patterning, contact over active gate, single dummy poly on an advanced FinFET node. The combination of all these features says that our 10 nanometer technology will be a full generation ahead of what others call 10 nanometer. Some roses, in fact, do smell sweeter. Of course, a modern microprocessor contains more than just logic. It is dominated by logic, which is why the correct metric is to look at the logic transistor density.
It contains more than just logic. You have analog circuits, I/O circuits, SRAM memory circuits. This graph shows the SRAM memory offerings on our 10-nanometer process technology. For the last many generations, we've offered a range of SRAM memory cells to service either high density, low power or low voltage or high-performance circuit applications, and our 10-nanometer technology is no different. We offer high density, low voltage, and high-performance versions, and each of these is scaled roughly 0.6x in area from our 14-nanometer technology. If you add it all up, what does a full chip scaling look like on our 10-nanometer technology? What I'm showing here is a representation of a typical Intel product.
If I look at our client products, our server products, and I take all of the different circuit elements and their weighted usage, I/O, analog, memory, logic, and I go through and estimate a weighted average improvement for a typical Intel product, you see that our full chip die area scaling is about 0.43x, significantly more than the traditional or normal Moore's Law trend of around 0.6x. The hyperscaling benefits of Intel's 10-nanometer technology deliver better than normal microprocessor die area scaling. Let me switch gears and talk about enhanced versions of our 10-nanometer technology. First, a little introduction. What I've said to you so far is that we are taking bigger steps than the traditional Moore's Law pace, but we're doing it at a somewhat longer cadence than the traditional 2-year cadence.
The net result in terms of density scaling is that we are on the traditional Moore's Law pace. However, the market still expects improved products on a yearly cadence. In order to support that, we need to provide improved versions of our 14-nanometer and 10-nanometer technologies, so we provide improved performance, improved power within a given technology node. This is what's shown here. Mark showed this slide. We're on 14, we provided 14+ and ++, and the same thing is true on 10. We plan to provide 10+, and 10++. If you look at our 10-nanometer technology first, compared to our 14-nanometer technology, we continue to provide improved power performance relative to the prior generation.
You can see that comparing our 14-nanometer technology to our 10-nanometer technology, you can have either a 25% improvement in performance at the same power or a 0.55x reduction in power, almost half the power, at the same performance. We don't stop there. We provide improved performance within the 10-nanometer family, and here I'm comparing the initial 10-nanometer offering to the 10++ process that will be supported for future 10-nanometer products. You can see that we provide a further 15% performance improvement at the same power or a 30% reduction in power at the same performance compared to our original 10-nanometer offering. We provide enhancements within the 10-nanometer generation to allow our products to showcase improved performance on an annual cadence.
This slide shows some of the other features that we'll be adding to our 10 nanometer technology to make it a complete technology offering to span the rich range of products that Intel has to offer, both for our internal products as well as for our foundry customers. We plan to add all of the many features that are needed to build the wide range of products, from servers, to clients, to FPGAs, to other types of products, and span the full range on our 10 nanometer technology. Some of these features include Hi-Q inductors, high-resistance substrates, high-voltage FinFETs to support the high-voltage IOs that are needed on some of our products, as well as many interconnect options to trade performance, density, and cost, as well as precision resistors and other features.
All of these technology features are available for use on a product-by-product basis as the 10 nanometer technology moves forward. I've described to you some of the unique innovations in our 10 nanometer process technology. In particular, I've disclosed for the first time today some of the key innovations in our 10 nanometer technology, including self-aligned quad patterning, contact-over-active gate, and unique process innovations that allow single dummy poly on an advanced FinFET technology. I'm going to return to the theme of hyperscaling that Stacy and Mark introduced and that Ruth explicated in her 14 nanometer presentation. Hyperscaling is really a technique that allows Intel to continue the economic benefits of Moore's Law. It features logic transistor density increase that is significantly more than the traditional 2x Moore's Law pace, albeit at a longer than two-year cadence.
It does afford the same rate of transistor density increase per year as traditional Moore's Law scaling, and the same rate of cost per transistor improvement as traditional Moore's Law scaling. This is really, really important. The economic benefits of Moore's Law are intact. In addition to service the needs of the marketplace for an improved product on a yearly cadence, we provide improved power performance enhancements within each technology node. Let me come back to this. Why do we choose to hyperscale? It's because of what Ruth explained earlier. 193 nanometer immersion lithography with a single pass can only get you down to an 80 nanometer pitch. If you want to scale below 80 nanometers, you have to have more than one pass through the lithography and etch tools. When you do that, you add to the cost of fabricating the wafer.
If you don't scale faster, you don't make up for that cost. To maintain the economic benefits of Moore's Law, we have to invent these new patterning schemes to extract the full cost per transistor benefit of those multiple passes through the lithography tool that you are going to pay for regardless. Hyperscaling really would not be possible without these innovations. These include self-aligned dual patterning at the 14 nanometer node, self-aligned quad patterning at the 10 nanometer node, along with some of the other innovations that I've disclosed for the first time today, contact-over-active gate and single dummy poly with an advanced FinFET transistor. These hyperscaling innovations really allow Intel to continue the economic benefits of Moore's Law. This results in this slide, which you've seen now multiple times. Moore's Law is alive and well at Intel. Let me conclude.
Intel's 10 nanometer process technology has the world's tightest transistor and metal pitches. The tightest pitches in the industry, along with unique hyperscaling features, contact over active gate, single dummy poly that really provide us leadership density. We believe our 10 nanometer technology will be a full generation ahead of what others dub 10 nanometers. We support enhanced versions of our 10 nanometer technology to provide improved power performance within the 10 nanometer technology. We do expect our 10 nanometer technology to commence manufacturing in the second half of this year. Returning to the theme of hyperscaling, Moore's Law has been a reality, an economic reality for us for the last 40 or 50 years of this industry. Moore's Law is alive and well.
Hyperscaling techniques allow us to extract the full value of the multipass patterning schemes and allows Intel to continue the economic benefits of Moore's Law, which has really revolutionized our whole world. Thank you for your attention.
Please welcome back to the stage, Mark Bohr.
Good morning, again. I'm really excited because today I have an opportunity to disclose for the first time details of our new 22FFL technology. What is 22FFL? 22FFL is the world's first FinFET technology for low power IoT and mobile products. It uses advanced FinFET transistors based on proven 22 and 14 nanometer features, provides a transistor option with more than a 100X leakage power reduction. It uses simplified interconnects and design rules based on 22 nanometer technology, offers new levels of design automation, RF design enabled, and it's cost competitive with other industry 28 and 22 nanometer planar technologies. This table describes or illustrates the design features we either pulled in from 22 or from our 14 nanometer technologies for this 22FFL process. Of course, all three of these technologies use FinFETs.
Intel has been manufacturing FinFET products since our 22 nanometer generation back in 2011. Starting with fin pitch, that's one key feature we pulled in from our 14 nanometer technology. We use a fin pitch of 45 nanometers, slightly relaxed from the 42 nanometer fin pitch used on 14, but the same narrow tall fins, the same high performance fins that we are presently shipping and have for a while now on 14 nanometers. Gate pitch is relaxed a bit to 108 nanometers. We have a wide range of options for different gate lengths within that pitch to best tune the design for either high performance or low leakage. We use a 90 nanometer interconnect pitch. That's not only cost effective because it uses single patterning, but has good design rule flexibility.
We have a 630 nanometer cell library height that's shrunk from our 22 nanometer process. This technology delivers using the metric I described earlier, 18.8 mega transistors per square millimeter. Higher density not only than our own 22 nanometer process, but higher density than any other 28 or 22 nanometer technology. The SRAM bit cell size is 0.088 square microns. Again, this process is based on proven 22 and 14 nanometer features. This technology offers a wide range of device types and features. It offers high performance transistors, ultra-low leakage transistors, high voltage I/O and power transistors. These transistors provide good device matching, low one over f noise. We also provide a deep n-well isolation feature along with precision resistors, thin capacitors, a high resistance substrate, and high Q inductors.
Again, 22FFL provides a wide range of devices for both digital and analog and RF design. These are two graphs that I first showed back in 2011 when we first introduced our 22 nanometer FinFET technology. These graphs illustrate the benefits of FinFETs over any planar transistor. The left-hand graph is a plot of a transistor gate delay on the vertical scale versus operating voltage. Obviously, a lower on the vertical scale means a faster transistor and a lower operating voltage moving to the left on the horizontal scale provide
The lower active power. That graph, again, shown way back in 2011, shows what we then called the Tri-Gate, and now we call our FinFET transistors, can provide better performance and power than any planar technology. Graph on the right shows channel current or leakage current comparing planar versus Tri-Gate. FinFET devices are a fully depleted transistor, which have a steeper subthreshold slope, and thus can provide lower off-state leakage than any planar transistor. Here I'm showing the high-performance transistors offered on 22FFL and comparing them to our previous 22GP technology, and comparing also to our latest 14++ technology. Plotting leakage on a vertical scale versus a drive current on a horizontal scale. Obviously, being down and to the right means a better transistor. Our 22FFL transistors are clearly much higher performance than our 22GP technology. On the same line, roughly as our 14++.
Similar drive currents to what we offer on our 14++ technology. Now let me expand the vertical scale a bit. I add the special low leakage transistors that are offered on 22FFL, and they provide leakage that is more than 100x lower than on our low leakage 22GP technology. Let me stress an important point on this slide. The vertical scale is not just subthreshold leakage, which is what you normally see on graphs of these types at the technical conferences. I am plotting on a vertical scale total leakage, which includes all three of the leakage components on a transistor. Includes subthreshold leakage, includes gate oxide leakage, and also includes junction leakage. When you get down to these really low leakage levels, all three matter. All three need to be carefully engineered and optimized to get us down to that very low leakage level.
That the low leakage devices offered on 22FFL are the lowest leakage transistors for any mainstream technology. Let me zero in on the two families of transistors that we offer on our 22FFL. We have the high-performance transistors that I described earlier, and those are on the die, of course, to provide high-performance logic, such as high performance cores. Coexisting on the same die at the same time are the low leakage devices down there in the lower left. Those devices are typically used for circuits that do not care as much about performance, but really care about ultra-low leakage. An example of such circuits would be the always on, always connected devices for circuits that you have. On 22FFL, you really have a very broad range of transistor types, from high performance to ultra-low leakage.
This technology is supported by Intel Custom Foundry and our robust ecosystem. We provide design services, soft IP, advanced IP, foundation IP, and design tools and flows. This is my final slide. The 22FFL provides high transistor drive current similar to Intel 14 nanometer. Provides special low leakage transistors with more than 100x lower total leakage than 22GP. Die area scaling is better than in 28 and 22 nanometer technologies. We offer a wide range of advanced analog and RF devices. We make extensive use of single patterning for affordable ease of design. We have ensured high yield with the use of proven 22 and 14 nanometer features. We are cost competitive with other 28 and 22 nanometer planar technologies, and industry-standard design kits, and the PDK 0.5 is available now, and the PDK 1.0 will be available in the second quarter of this year.
The second will be ready for production in the fourth quarter of 2017. Again, my final summary statement is that 22FFL is an exciting new technology that provides a compelling combination of performance, power, density, and ease of design for low power IoT and mobile products. Thank you again for your attention.
Please welcome President, Client IoT Business and Systems Architecture, Murthy Renduchintala.
Finally, somebody pronounced my name right. I'll have discussions with Stacy and Laura after the event. Maybe we'll sit down and go through the syllabic deconstruction of my surname. Good morning, everybody. It's really great to be here. I hope you found this morning a fascinating three hours of technology exposition. I have the great fortune and incredibly exciting opportunity that together with my colleagues in the product division to work with all the goodness you've just witnessed and create leadership products. The role I have at Intel offers me an exhilarating challenge to drive both business and technology. On the business side, I'm responsible for Intel's Client IoT, connectivity, and automated driving businesses. Together, they account for about 60% of Intel's revenues.
On the technology side, I'm responsible for the company-wide systems architecture organization, which consists of all of our silicon engineering, our platform development, and software enablement. Very importantly, I'm also responsible for working with Stacy, Sohail, Ruth, Mark, Kaizad, and many other brilliant people in our Technology & Manufacturing Group to align our process and product development roadmaps. In my talk today, I'll touch on three topics: product cadence, advanced silicon design methodologies, and the benefits of Intel Custom Foundry strategy to Intel's product businesses. All of these are emblematic of a new way of describing Intel's product roadmap. For that description, we're going to do away with the tick-tock metaphor and replace it with a metaphor based on waves of innovation.
The metaphor is built upon the principles of predictable annual cadence, co-optimized process, architecture, and IP, delivering compelling user experience improvements to drive an acceleration of product refresh. It's important to recognize the products are not exclusively associated with a node transition or a process optimization. Certainly, the innovation that Stacy and the team produce are a huge part of what we do. Nor could we produce world-changing products by relying on architecture and design alone. The wavefront of compelling products is formed by the intelligent application of all the technical vectors Intel has at its disposal. Perhaps to overuse the metaphor, waves do strike the shore. If we view the market as the shore, when the wave strikes, we get meaningful reasons for product refresh. Let's dig a little deeper into the principle of cadence.
For those of you that were Investor Day, would've heard me already say this, I think it's a good set of lines, I'm going to use them anyway. At Intel, there's a fusion between process technology and product development, resulting in customized transistors and IP libraries for specific product segments. The tailoring of our process technologies to our product requirements provides us with performance leadership that exemplifies the strength of Intel's IDM model. For example, we're able to use different transistor flavors to meet the specific power performance and area requirements of our central processing unit needs and our graphical processing unit needs in our core roadmap. This tailoring of performance leadership encompasses the entire portfolio of Intel's products. We're able to optimize our process and products within a technology generation to deliver meaningful performance and maintain an annual product cadence. Let's supplement the rhetoric with reality.
As we move through our 6th, 7th, and 8th generation cores, we're delivering significant performance improvement on important industry standard benchmarks. We've realized all of that with substantial improvements in power performance as well as we've developed our product range on 14 nanometer. These improvements are made by a combination of continued 14 process nanometer enhancements that Mark and Ruth touched upon. Most importantly, products are being delivered using this technology on an annual cadence with waves of process, architectural, and design innovation to stimulate refresh. Our products are really only as good as their constituent IPs. Our process and product teams work together to ensure that IPs map to the right technology wave. In fact, we stay on a node longer because it has utility across a wider range of products and IP.
At the same time, as we transition from 14 nanometer to 10 nanometer for our core roadmap, we're bringing our modem, our networking, our FPGA products into 14 nanometer. Our Stratix line of FPGAs is already in production in 14 nanometer. Our LTE and 5G modems will ship by the end of this year and through 2018. The IO chips that ship with our core products will be available by the first half of next year. Our networking products will ship in 14 nanometer through the course of 2018. We'll continue this pattern in future node transitions. As our core products move to node N+1, the broader portfolio will move to node N. Moving to the second topic of my talk, advanced silicon design methodologies. Let's examine a typical silicon product and de-pop it for a second.
The graphic behind me is not meant to reference any particular device or architecture, I think it's pretty typical of what the industry has traditionally done. It's monolithic, where all the IPs are constituted in the same process technology. As a result, all aspects of the chip have been implemented in a particular fashion, driven by the necessity of node convergence. That's pretty constraining to Intel because Intel has a rich portfolio of IP in an array of process nodes, all optimized to localize power, performance, and area, or PPA. This presents an incredible opportunity for Intel in creating heterogeneous SoCs. That has a profound impact on how we will deliver products to the market now and in the future. For example, we can mix high-performance blocks of silicon and IP together with low-power elements made from different nodes for extreme optimization.
Another example, we can mix logic together with field-programmable gate array technology to provide complex and adaptable functionality, which is going to be key for future technologies such as network functional virtualization and software-defined networking. Stacy highlighted, Mark further explained, our embedded bridge technology, or EMIB, in their talks. It's a truly transformational technology for Intel. EMIB is an intelligent, elegant, and cost-effective approach for high-density interconnect of heterogeneous dies. Unlike traditional multi-chip packaging, the interconnect, as Mark described, is running on silicon rather than through a substrate. The density of interconnect enabled by EMIB allows relatively simple circuits to be used to connect die together at multi-100 gigabytes per second transfer rate. In addition, we're able to deliver 4 times reduction in latency at that transfer rate and a 5 times reduction in power as compared to MCPs in general.
Intel's already brought this technique to market. The Stratix 10, based on EMIB technology, is already shipping. It consists of the world's first 14-nanometer FPGA, which is constituted of 2.8 million logic elements and nearly 1 million adaptive logic modules. It's interconnected via EMIB to up to 16 GB of in-package memory with up to 512 GBps aggregate transfer rate. It's also interconnected via EMIB to 144 high-speed transceivers, which can deliver an aggregate I/O transfer rate of up to 400 GBps. The exciting thing for me is that EMIB is no more than just chapter one of the heterogeneous SoC playbook that Intel is going to move forward with in the future. We'll share some of the evolutions in our thinking in this matter at periods in time when we're close to bringing those technologies to market.
Clearly, this is going to be a strategy that is going to play a large part in Intel's product roadmap moving forward. Up until this point, I've talked about how we've established an annual product cadences in all of our businesses and how we're using heterogeneous SoC construction to assist in this regard. I'd like to go back and amplify something Stacy discussed, and that's the link between our product business and our foundry. All the technology and IP I've discussed is available at our foundry, and it has the potential to be made available to our strategic partners and customers. The co-optimization and integration of Intel IP with that from third parties leads to leadership products, not only for our customers, but for Intel as well.
Customers gain the advantage of Intel's IDM capabilities and benefit from significant time to market and time to yield for their products. They also reap the rewards of working with the leader in process technology. I don't know who amongst you were at Investor Day, but at Investor Day, I used an analogy of artisanal baking to describe the linkage between process and product development. Truth be told, many really liked the analogy. I think a few didn't, but I'm going to continue with it anyway because I think it serves the purpose that I want to amplify today. At that time, I was really speaking about Intel's internal capabilities. The same principles are no less true in the custom foundry context. The flour we use to bake remains highly differentiated from wholesale.
As I said in Investor Day, we partner with the farmers and the husbandry of the wheat and select the best in order to create products from our bakery that have incomparable quality. With Intel Custom Foundry, we're enhancing and enriching the flour we use to bake, and we're expanding access to the bakery to other artisanal bakers. Our bakery is one where bakers learn from the skills of one another, such that everybody becomes a better baker. An Intel baker becomes a better baker because we're working with other bakers who have skills and IP and techniques to offer us. That is going to be a unique chemistry that we'll seek to amplify and enhance our product businesses with as we go forward. In closing, let me emphasize the key points of at least my pitch today.
The tailoring of our process technologies to our product requirements provides us with performance leadership and exemplifies the strength of Intel's IDM model. Our product roadmap has an annual cadence with waves of process and architectural innovation. The co-optimization and integration of Intel IP with that from many third parties leads to leadership products for both Intel and our customers delivered via our foundry. That is the IDM advantage. Thank you.
Thank you. We're going to bring up a couple chairs on stage before we begin with the Q&A session. As we're getting ready for that, want to highlight, we've got four mic runners for the Q&A. Raise your hands, Kara, Will, Trey, and Mark. They'll start roaming the rooms, getting ready.
Going to be pretty much dictated by what process flow you're using. Your biggest knob that you have for the cost is going to be density, and that's the part that drives everything. If you lost the density, then you have lost the ballgame. You just cannot recover that part by any means of cost cutting. That's the advantage we clearly have, as Stacy, guys out the room, everybody has shown that part. We have a very strong foundation on which we're building and providing better and different type of transistors that could be utilized with different products. In foundry, this is going to be a big item for us. Provides us a clear advantage over our competition.
A shout-out to a pro-investment policy in the U.S. The other big difference is the incentives, the tax structure, which dictates where in the world it makes sense to build these factories. Those are really the two. It's the density curve then the incentives you get. Everything else, it's a common set of equipment. It's relatively low labor content, the rest of it just washes out. I'll go to Trey. Then I'll come to Kara next.
Thanks, Stacy. It's John Pitzer with Credit Suisse. I guess my first question, when you look at self-aligned double and quad patterning, those were innovations in part that were driven by a delay in EUV lithography tools. I'm kind of curious, when do you think EUV finally comes into the fray, does that change sort of the competitive advantage you have with self-aligned double and quad patterning?
If you look at it, EUV is making good progress. Last couple of years, good progress has been made. Our position has been that we'll use EUV when it becomes affordable. We have the tools, even if you're running EUV, these techniques that you have, you will need it down the road in order to enable it. All that's happening is we have learned how to do this thing now. When EUV comes in, it will simplify things. Moving forward, further down the road, there's talk about High NA EUV, but that's 10 years from now or five years from now. These techniques that we have developed on immersion are going to all carry over and help us scale better.
Thanks. That's helpful. I guess as my follow-up, can you help us understand how quickly EMIB might penetrate your product portfolio? Might that technology be a driver of smaller die size over time at the wafer level, if you can do some of the integration very well on the back-end packaging?
If you look at it, we have a part out already. Stratix 10, which is our FPGA part, is the first part that we got out. We have lots of big plans around EMIB. It's a very enabling technology. As Mark and Murthy have talked about it gives us a lot of flexibility to be able to do different things. That's our internal innovation that we have, and we intend to use it as we move forward.
Murthy, do you want to add anything?
I think, John, what we've described today, I think, is the tip of the iceberg in the relevance of EMIB to us. I think it represents the first chapter, as I said, in a more generic strategy for us, where we go beyond the constraints of monolithic integration and look at multiple techniques of how we can essentially get the equivalence of monolithic performance, but without having to have the compromise of everything being in a single node. Many of you probably know in the audience, as you go from node to node, for example, from 14 to 10 to 7, there are many parts of IP that greatly benefit from that. Clearly, our CPUs and our GPUs really benefit from that.
There's a lot of analog circuitry and IO circuitry that actually is somewhat detrimented by being able to move in that scale because they're really focused much more on leakage as much as they are on performance. That juxtaposition is something that's always constrained our ability to move faster and with agile. Clearly, one of the key things on my mind is how I most effectively use Intel's R&D budget. What I don't want to be doing is spending a large amount of R&D porting IP from node to node that doesn't get any inherent performance benefit. The ability to be able to decouple that and have my R&D focused on absolutely competitive advantage generating capabilities is where I want to be. Move my CPU and GPU into one technology.
The other technology is how do I basically play maybe in a lagging node that gives me other performance benefits that allows me to get new products out quicker? That's the kind of thesis that we're driving inside. EMIB is just one of many techniques that I think you'll see us bring to the market in the future to show how we're really tackling that conundrum.
Kara?
Rick Merritt from EE Times. A question about your new 22 nm node. One for, I guess, either Ann or Sohail, if you could give any specific metrics about how it compares not to 28, but to the 22 nm FDSOI. My follow-up would be for either Stacy or Murthy to give some clarity on the products that you're targeting here. Is it mainly for foundry? Or if it's your own products, what kind of your own products?
This technology is offered both internally and externally. Internal product at this point, I don't think I'm going to talk about it, but there are products being designed on our 22FFL part. Compared to FDSOI part, there's nothing out yet. People talk about it. It's FDSOI, I've heard. It's a good technology, but we'll be going into manufacturing by the end of the year on a very strong baseline. Fundamentally, SOI, if you look at it, is a costly technology compared to the bulk, so it still has to be proven. What we are offering is, as Stacy showed in his slides, we have on our FinFET technology, we have already processed over seven million wafers and have shipped greater than half a billion units on 14 nm.
The offering that we have is far more compelling and based on very strong technology that we already have on hand, versus somebody might be making promises in the future.
I'd like to add, as somebody that was involved from the very foundational definition of 22FFL, we didn't develop that process as something we wanted to put on the shelf for a foundry. We developed that process because of the diversity of our product range and the need to get into processes that were really focusing on ultra-low leakage, as well as elements of our portfolio that needed high performance. For us, it's very much going to be a fundamental part of our roadmap going forward, because our roadmap going forward is going to be much, much broader than maybe what you've traditionally expected of Intel. Moving into IoT, into mobile, into networking, where clearly the attributes of 22FFL are going to be really, really enabling for us to give differentiated performance.
Again, when we specced 22FFL, we had a clear understanding of where 22 FDSOI was going to go. I think it's going to be a valuable node, not only for the internal divisions, but also the foundry, to provide a compelling diversification of options out there for parties who want to go for ultra-low leakage implementations.
Internally, just think of a world where we now have an ultra-low leakage process. We apply our leading-edge capabilities to ultra-low leakage, then we have EMIB capabilities to start to put heterogeneous pieces together in a single product. It really starts opening up a lot of capabilities for us as you think about that going forward. Kara, again. Or nope, she's delegating to Trey.
Thanks very much. Chris Hemmelgarn, Barclays. Could you just talk a little bit about the opportunities EMIB opens up for combining Intel products, say, your modem with external foundry customer products like an apps processor or even opportunities for combining an FPGA with some of your server products?
Yeah. I think you're going to the same territory of just looking at the panoply of opportunities we have with EMIB. I think it's also cautious to say, look, MCP is not going away. There are going to be applications where MCP makes perfect sense. There's also going to be a situation where, for example, maybe because of the thermal density of certain pieces of silicon, putting them into one package may not be the right physics. We'll use high-speed interconnects such as PCIe or other techniques to deliver that. There are going to be a number of opportunities where embedded silicon bridge is going to be transformative in the properties that we could deliver. Therefore, again, it gives us a lot of options in terms of thinking about how we deliver the equivalence of monolithic performance.
Modem, AP, memory, logic, are just a few examples of what you could think of. Clearly, the Stratix 10 has showed how you could put FPGA together with high-speed IO, together with embedded memory, all in one package using silicon bridge technologies. That gives you pretty much close to monolithic levels of performance. All of those are on three different technologies. You can basically take third-party memory and put that in that package. Not all of that technology necessarily has to be from the same source. They can be from a mix-and-match approach.
Got you. Just to make sure I heard you right, you're definitely very open to taking third-party IP, third-party blocks, and combining that with fully in-house Intel stuff-
Yes
in foundry. Okay, thank you.
Actually, if you look at Stratix 10, that's what we're basically doing. You have SerDes coming from outside and the rest of the FPGA is coming from inside.
Kara?
Hi, it's Nico with Golem.de. I hope you could shed some light on how you managed to get the contact on top of the active gate. Does that have to do with the larger fins that you're using in the evolved processes in 14 nanometers?
I'll let Sohail take that one.
I don't think that's our sky-dance plan to go into the specificity of. We just laid out this as a structure, we were not going to go over the detail of how did we do it.
Okay. Point taken. On the new silicon interconnect EMIB, would that also give you an option to have a more cost-effective construction of Xeon made up of multiple dies?
That's a great idea.
You've been doing that.
I wonder if other people.
for over two quarters, right?
All right.
Two very good questions for which we're not answering. I like it. Where are we? I see Mark. Yep.
Hi, this is Stephen Chin from UBS.
Hi, Steve.
Yeah. A question on the hyperscaling and the cost implications to CapEx. Given the additional improvements over the longer life of nodes, is there higher CapEx intensity over the full life of that node as a result, for both 14 and 10 nm years?
Yeah. I'll refer you back to some information that Robert Swan showed at the investor meeting, which was a month or so ago. He showed, take memory investment to the side. He showed overall capital investment as a percent of revenue. What it says is that it stayed pretty constant. It stayed with what I'll call inside the historical band. If you think about this, the curves that you saw from several of us answer the question. The cost per square inch of silicon goes up. We get more scaling. That allows us to do more products per dollar of capital spent. At a constant volume level, we can stay pretty constant in terms of overall capital intensity, is the way I would think about that.
Great. Okay, my quick follow-up, for EMIB, for that silicon bridge that was shown in the pictures, is that silicon bridge? I can't remember if the detail was mentioned earlier. Is that being manufactured by Intel, or is that coming from some other third-party supplier?
We have an IP on it, and it's manufactured externally.
I think two more questions, if there are two more. There's one up front here.
Ian Murphy, Enterprise Times. One of the new challenges we've got is IoT and security. With connected cars in particular, we've got the problem of a whole ecosystem where a manufacturer does not know who else is going to connect to it. What are you going to start bringing down into the new chips in terms of security components to authentication and device, how do you actually verify and authenticate that either the generator of or the consumer of data is actually a valid and authenticated node on that network? Intel has technology that it's basically developing. It goes by the acronym of EPID. I can't expand the acronym, I'm sorry.
Yeah.
It's a great technology. I know where we're using it, and it's basically very much targeted towards enabling device authentication and attestation. Quite frankly, I think it's IP that doesn't necessarily have to be only in Intel part. I think it's our contribution towards this whole discussion on how we essentially get security in the IoT environment. There are other options out there. I think the key is really being able to have any network infrastructure that's hosting an IoT application to have confidence that it's communicating with valid or authenticated IoT client devices. That's going to be, I think, a very important piece of technology to enhance IoT. I don't think it's going to be gate heavy, but I think it's going to be needing to have a broad-based discussion around it to make sure there's a degree of industry-wide consensus on how we deliver that.
We've put some ideas into the pot. I'm sure others will, and it's a problem that I'm absolutely certain will need to be resolved for IoT to scale.
I apologize. I'm having trouble seeing the timer, and I was going to cut y'all short. We can actually take one more question after this one, also, and still live within the time, and then get you to lunch. This question and one more, and then I think we're officially out of time. Is there? Awesome. Oh, wait. Okay, Trey?
David Kanter again.
All right. Welcome back, everyone. Hopefully, you guys enjoyed the lunch. Very excited to bring this panel discussion to you today. I'm Zane Ball. I'm a Co-General Manager of our foundry, along with Siva there at the end, and we're very proud to have a very distinguished group of folks from the industry to talk a little bit about Intel Foundry. We have Will Abbey here from Arm. He's Senior Vice President of Strategic Alliances and Sales. We have Lip-Bu Tan, President and CEO of Cadence Design. We have Aart de Geus, who's Co-Founder and Co-CEO of Synopsys, and Siva, my partner managing the foundry. I thought we would just get started today. I have a little cheat sheet here with some of my questions. I thought I'd just get started today.
We heard a lot about Moore's Law being alive and well at Intel. Certainly Intel's traditional businesses have always benefited from being on that leading edge. I wanted to get the panelists' thought around what that Moore's Law progress that we heard about today means for foundry customers. Why don't we start with you, Will?
That's the benefit of sitting next to you.
Get Arm and Intel together. You never know what's going to happen.
We at Arm, we're super excited that we're in collaboration with both Intel and Cadence on both 22 nanometer and 10 nanometer technologies. On 22, 22FFL, we think that's a really exciting technology for multiple reasons. One, it offers the benefit of a FinFET transistor. You've heard a lot of that being talked about this morning, and also the fact that it has a simpler back-end of line process. The benefit from an Arm perspective is that we think that will provide a fairly compelling migration path for our high volume, cost sensitive partners in both mobile as well as consumer. We think that as we couple that technology with the physical IP implementations that my former group are working on, targeting our next generation ARMv8 Arm cores, we think it'll offer a differentiated offering to the market.
As I look at 10 nanometer, clearly you've heard a lot said about that. I'm not going to echo any of that. As we work through the implementation of 10, we can clearly see that it's going to offer compelling performance benefits. Particularly on the density side, as we continue to look at the implementation options, we can see that there's going to be a clear density benefit beyond the so-called 10. We think that you guys are underselling the capability of the technology by labeling it as a 10 nanometer node. We can see 10 being a good candidate for our next generation high-end ARMv8 cores targeting both mobile and high-end mobile solutions. We think that Intel, coupled with the work that EDA partners are doing and IP partners are doing, is clearly focused on bringing differentiated value to the foundry space.
Think so. Lip-Bu, anything you'd like to share there?
I think this morning you heard that in their process technology, their packaging technology, and also clearly in the low leakage and low power, I think it's a great benefit for our fabless customers and the mutual customer. I think they see that they really can lean on the ICF to do that, so that they can really focus on their design content. That's number 1. Number 2 is clearly, there's a massive investment into the foundry that they can lean on and they benefit from it with clear, unique technologies. The other part is they also can further benefit from the Cadence, the tool and IP optimized for the process node that Intel is driving. We're excited about this collaboration.
Aart?
You asked about the future of Moore's Law in Intel's hands, leadership is something very difficult in this field. Many companies don't achieve this, Intel has for many decades, which is amazing in many ways. The presentation this morning gave an insight of this so important trio of PPA, performance, power, and area. Area is sort of a substitute for ultimately the manufacturing cost when you multiply it by yield. What is so interesting is the balance of how these variables keep being moved forward at the very moment that the entire market is just hungry for being able to give more performance with lower power because everything is portable, everything needs to be in power-saving mode.
The very fact that we came today we have already optimized a number of Arm cores in these new technologies very successfully, of course, we've done it with Intel for many years on the heavy-duty processor cores. It's not only PPA, the third and fourth variable are really risk management and optimization, which is all the things that you do around it. This is where the partnership with Intel has to be as good as we can make it, because every time that we reduce the risk, it gives more opportunities to customers. Every time we can do a better optimization, be it on the technology or be it on the IP, we actually add value to what our joint customers will do with it.
Siva?
I'm super excited to be here. Thank you for being a part of this. ICF, as you heard, is focused on leading edge 20 and below. Here, we are offering Intel's crown jewels to be shared with our foundry customers. That is super exciting from a foundry customer standpoint, having that choice. At ICF, our focus is to offer industry-standard IPs and tune them right from the get-go on PPA, which is performance, power, and area optimization. We do that while the process technology is in definition so we can actually tune that. Second is, with all the EDA ecosystem partners, we co-optimize the solutions to make sure they have a choice. Whatever may be their selection criteria, they have the full choice. At the end of the day, they have to make that decision. Same thing with the design partners.
You've heard, to our portfolio, we've added 22FFL, that is another great addition to broaden our portfolio of offerings we have. Really looking forward to a great future ahead.
All right. Thank you, guys. Aart, next question for you. We just announced this 22FFL today, kind of big news, Intel putting more effort into more mature technologies. What do you think the opportunity from a foundry point of view is for this technology?
I think the opportunity is great. It's big news, of course. We've been working on this now for a long time to make it work well together. It's big news because I think this technology happens to hit one of the most important sweet spots, which is this intersection between the ability to go for high performance, but also to drive down leakage or any other form of power as much as possible. You only have to look around at the world of mobility, of portability, but also on this coming wave of digital intelligence, which will drive semiconductors like crazy, and it has one demand, which is give me more performance and less power. This technology has the potential to hit the sweet spot and be adaptable on the curves that you saw.
Now, in order to do that, a lot of effort went into making sure that the design flows are ready, that the IP is rolling out as needed by the customers when they need it, and of course, that we can support the customers in different places in the world. The good news is, we've already taped out quite a number of chips together with ICF, there's good evidence that we are ready.
Thank you. Lip-Bu, we've been working together in the foundry. How would you describe our collaboration and what kind of progress do you see us making in this new initiative?
Sure. A couple of points. I think one, clearly, we significantly increase our collaboration together. On the depth and also in width, clearly on the 22FFL and also the 10 nanometer, I think those are great opportunity we work together and all the different process node and how to optimize based on your process node. The other part is also in terms of the more depth is basically we share common customer requirements so that we can really drive the performance and the power or the PPA performance, to meet the customer requirements. I think that is a very important point.
The other part, I think, is clearly the deeper engagement and support the third-party IPs, like we have worked closely with Arm and also some of the Cadence interoperability, interconnect IP, and memory IP, so that we can really serve the customer better. I think that's a very important point. There are a few teams have been working together so that we can serve the customer in the local expertise and then plus the different experience that we can support locally the customer well. I think that's very important. Clearly, I think overall in terms of how to really drive the performance tool in the more better way to serve the customer, I think that is a critical important to the customer. At the end of the day, we are supporting our customer.
That's right.
Make sure that they tape out correctly and then meet the schedule that they require. I think that needs a very deep collaboration from the IP point of view, from tool point of view, and also from the foundry. I have to say that I think the service orientation from ICF has significantly improved, and we see that, and the customer love it. You have a lot of technology to offer to the customer.
Thank you very much. Will, our relationship is pretty new. We've been working together for less than a year, but it's been an intense collaboration. What's your take on Intel's ability to compete in this foundry space?
I think that's a really great question. In fairness, we have been working together now for 10, maybe 11 months. It's unquestionable that Intel has great technology. We've heard it played out today very eloquently. I think an important ingredient that's needed to be successful in foundry is a customer-centric mindset. We went into this journey together wondering whether Intel would embrace what we believe to be a successful ingredient that's required to make a big difference in the foundry space. We're pleased that as we've asked questions of Intel in terms of looking at the mosaic of different customer needs, Intel has responded very, very well. As we work together through those questions of design methodology, EDA tools, EDA views, EDA design capability, we've been pleasantly surprised on two fronts.
One, not just the capability of the Intel engineering and strength and depth, but also the willingness and openness to adopting new approaches and new ways of working. In a recent meeting that we had, I remember sharing with both Siva and Zane that I think you've come to a point where you can really ask yourself, does ICF really describe what you guys are all about now? Because the C for me stands for custom. The fact that you've embraced this notion of a standard methodology, a standard approach, I think that you should reconsider whether ICF is a good description for where you want to be. I'm pleasantly surprised.
Intel Standard Foundry or just Intel Foundry. Forget all the marketing advice I give.
Either Intel Foundry or Intel Standard Foundry. I think that, one, we've been pleased that you've been open and receptive to working with us in a way that we think it's needed to be successful in foundry. I think that you're ready for big time as far as I'm concerned, right? Foundry is the ability to support a mosaic of different requirements, a mosaic of different customers. With the work that we've been doing together, I think you're now ready for prime time.
Thank you. Well, certainly we've had a lot to learn entering this new space. Siva, question for you. You and I started managing the foundry together just about coming up on that two-year anniversary pretty soon.
It's coming up.
There's been a lot of things that we've learned as we've gotten into this. What are some of the highlights for you in working with our external environment?
Yeah. It's been a pretty exciting ride. I would say two things really stand out in the learnings. First one is at the customer selection stage. First, the customers want to make sure they have the IPs that they're interested in available. That's the first one. The second one is to make sure those IPs are tuned, well tuned. We call it co-optimization at Intel. Murthy used the phrase fusion. Whatever word you use, is really make sure the power, performance, and area are fully optimized to take advantage of the features that you've heard today. That's the second one they look for. That's only the selection criteria. That's a starting point. It gets you started. After that, it's really about understanding the customer needs and how they want to differentiate themselves in the market that they have, and how can we fine-tune that.
In that journey, in the IP portfolio, one of the key things that we have heard is how about the Arm CPUs, not only today's but the future. As you've heard in the last IDF in August, we've added to the portfolio. Will was mentioning a dialogue he was having with Zane and myself recently. The key part that I want to highlight in that conversation, they were asking the methodology, should it be tuned and should it be standard? We insisted that it should be EDA standard recipe that gives the choice and the power to the hands of the customer. The key leading solutions both are optimized and standardized so that the customers can take full advantage of it. We made that crystal clear, and that's what it's all about. I think it's about making the customer succeed.
That means they're getting the best results on our technology. They have the choices in their hands. Third is we are open to co-optimizing the solutions to solve their specific problem. TD organization has been extremely open in the, what I call the last mile, to bring the optimizations, in addition to the technological features, to make our customers win. That has been really the learnings for me. We're super excited that we have all the support we need from the ecosystem partners and the technology development inside to actually serve our customers. That's been my learning.
If I can.
Great
I want to stress one of the important point, which is, the proof of the pudding is always in the tasting. Both from a 10 nanometer and 22FFL collaboration that we're working on together. End of the year, we're going to have our first silicon tape out on 10. I think the benefit of that is that our partners, our mutual partners, will be able to take the solution that we've co-developed and actually see if they can replicate that PPA, which we think will be compelling in the shortest possible time. That's both from a 10 nanometer perspective and also on 22FFL, we're targeting a low leakage, high performance solution for Q1 of 2018. Again, it's about standard methodology, standard EDA flows. Can you reproduce that in the shortest possible time?
I think all our partners in the industry will be able to see whether the work that we've been doing is just smoke and mirrors or whether it's real, and we think it's going to be very interesting and very compelling.
I'd like to add to that. It's been interesting to observe the learning of ICF engaging with customers, because you can do everything right, but you have to earn the respect of the customer. Obviously I won't share details, but ICF does have the first repeat customers. You never get a repeat if it didn't work out, right? People watch you in the first engagements very carefully because ultimately this is all about predictability of outcomes. It is very complex what we do together, a single issue can jeopardize the work of the entire group here in no time. The fact that you have repeat customers that are engaging on the next node, on new technology, on new cores, I think is a very good sign. I would encourage to continue that rapid learning.
Thank you.
Thank you.
Okay. I'd like to maybe turn the topic a little bit to bigger picture. We've heard a lot of things today with the advance of Moore's Law and very sophisticated items going on with contact over active gate and self-aligned quad patterning. Very sophisticated stuff. Obviously, Moore's Law is getting more difficult. It's getting more expensive on the design side, to achieve these remarkable benefits of better transistor density and that drives our industry. We have to work a lot harder for it. There's more R&D required across the industry. I think that's starting to change the structure of the industry as well, right, and with consolidation and things like that. I would love to hear each of your thoughts on what you think the future industry structure with foundries look like. For bonus points, where you think an Intel foundry could fit into that.
We all know the rich history of the fabless ecosystem, but I think it's changing a lot going forward. Whoever wants to jump in first.
Sure. Well, for starters, the fact that things are more complex, complexity is our middle name, right?
Right.
That's what we've made a living of. Moore's Law has been dead so many times you wouldn't believe, yet here we are.
Right.
Secondly, you say it's more expensive. It is. Complexity does bring expenses, you see a consolidation of the market to players that have the ability to continue to invest and survive over time. I would add that I think we're entering a phase of the electronics market that is as interesting, as driving as the computational era was in the '80s and '90s, the whole mobility era was, now we're going into this era of smart everything. If there's one thing that these eras have in common that helps right now in this business is what's better than smart? Smarter. How do you get there? Well, better algorithms.
Really what we would like is another 10x more computational power or 100x as a matter of fact, it will open up the door, I would argue that the cost, as much as one has to deal with it, is not at all the issue. The value is so high that even if the chips were twice as expensive, I'm not suggesting you do that, it still would absolutely be driving things forward. In that context, a foundry that can execute at this point in time has an enormous potential because there's so many people that are coming up with fabulous software ideas around digital intelligence that if you can support them with the hardware that can deliver more performance at low power, I think you're going to be in a great spot.
Just to add on to it. I think clearly the complexity has increased a lot. Depend on what are the vertical market you're going after. Some of them clearly like mobile, power become very important, and low power leakage, and density become critical because cost is very important. At the end of the day, it's the first time pass is critical. Anytime you do a respin, it's just costly. Time to market is critical. I think that execution requirement and also some of this advantage that you have, how to put it together to support the customer and some of the vertical have different requirement. Intelligent on the edge, clearly everybody talking about that whole industrial revolution is a huge opportunity.
You look at the machine learning, deep learning is a huge broad application along the way, either to automotive or the cloud infrastructure. All these have different requirement, and that's where I think from Intel point of view, how to drive some of this differentiation to show at the end of the day, customer success is everything. Time to market, the performance, PPA at one time is critical.
There you go.
Okay. I guess it's left to me. I mean, as I ponder the questions, a wise man once said that nothing new under the sun, right? In order to predict the future of the foundry space, I think the best place to look is look behind us and look where we've come from. I guess for me, the important point is that
Intel now entering into the foundry marketplace, I think you're going to bring great technology. It's also playing in foundry is not a cheap game. It's a high cost, a high investment, and Intel is not short of capital. I think if we look at our rich heritage and where we've come from and how innovation has come about through competition, I think the fact that we now have another significant play in the foundry space, I think that foundry is in a good set of hands. We've heard a lot talked about the new emerging application areas of a smarter, connected world, whether that's automotive or whether that's in the home. I think that's going to bring a diversity of applications, a diversity of opportunities. As we see more competition, we've heard a lot talk about 22 already this morning.
There are multiple players now on 22. We've seen the same on 10 and below. I think foundry is in a good set of hands. We will continue to do our part in terms of EDA partners and IP suppliers to ensure that solutions are available for the rich potential of application areas that exist. From an Arm perspective, we pride ourselves on multiple choices and enabling choice. We don't want to see a world where our partners only have limited choices for technology or limited choices for manufacturing excellence. We think that Intel coming in is just going to allow the foundry space to become a lot more competitive. It will drive more innovation. Foundry space is going to be around for a long time. From an Arm perspective, we think it's a really good thing.
I'd like to highlight three things that really excite me. The first one is Intel technology. Mark talked about how he actually is spending his time on the next after seven, what we call the seven. The Intel ecosystem has the technology investment to keep going. That's number one, that everybody can count on. Second thing is, compared to a pure-play foundry, Murthy talked about how he called that the bakery, where we can actually share ingredients and the IP, the richness of the IP that we have, we can actually offer in addition to the industry-standard IP. That I think is a differentiator that we alone can provide. The third thing that's really exciting is optimizing all of this with an EMIB kind of technology, where you can actually mix and match, you can have the cake and eat it too, so to speak.
You have the low-power applications on one technology node and performance-hungry, density-hungry applications such as CPU and GPU and put them together. I think that gives a very exciting choice in the world where it is really accelerating the number of applications we're seeing, and that gives an incredible choice that I hope that some of the customers will take advantage of. I'm super excited to see that.
Okay. Well, I think we'll wrap it there. Just a couple of comments. Something I've learned in being part of this foundry effort is that it takes an ecosystem coming together to make the fabless customer successful. Intel's traditionally been very much the iconic IDM, that works very much under our own roof with the help of a few partners. We only succeed when people like you guys that graciously joined our panel today work together. I think we're learning this game, and we wouldn't be able to have gotten to where we are without your partnership and support. Please accept our very big thanks on behalf of Intel.
Yeah. Enjoying seeing the team, all of you. Appreciate your time and presence.
Thank you.
Pleasure.
Thank you.
Most importantly, partnership.
Thank you.
Thank you.
Great. Thank you.
Well, thanks.
Thank you.
Ladies and gentlemen, thank you for attending the Intel Technology and Manufacturing Day. Please welcome to the stage Vice President, Finance, Director Investor Relations, Mark Henninger.
Welcome back, everyone. Thank you for joining us again. We'll be doing a Q&A, and I'm going to invite a few folks to join us up here, Ruth, Murthy, and I'm going to avoid the risk of mispronouncing surnames by going with.
Howard.
just first names. Yes, Howard, indeed.
Rajesh Intala.
Mark and Kaizad.
Mine is short, but you'd always get it mispronounced, too.
We've got a few minutes for some Q&A here. What we'll do is we'll do one question per person, as is our custom. I'll just remind everyone briefly, too, that we are in the quiet period, so we'll try to limit the scope of the questions to the technology and announcements that we have here today. Without any other delay, why don't we go ahead and kick things off? Why don't we start right here. Ross.
Hi. Ross Seymore from Deutsche Bank. Murthy, you've mentioned going from a tick-tock to more of a wave in your product innovations. Can you just talk a little bit about the challenge that happens every three years where a node-based product line hits upon, I guess it would be the plus-plus product line, and how strategically Intel stacks those in to avoid cannibalizing and all those sorts of issues?
Yeah. First of all, I think we take a fairly long-term view of planning our roadmap. We sit down as a team on the product side and with colleagues such as my three eminent colleagues here, and talk about where are we in terms of the intra-node movement as well as the new technology nodes that are coming up. We look at the relative performance increments that are coming out of process. We match that against where we believe we're coming up with improvements in architecture or IP-derived benefits.
We have a clear benchmark around which we want to improve performance on a year-by-year basis. We dial in the right chemistry and the right degree of risk profile for how we deliver on that. Then lock in which node with which relevance of IP and which architectural framework go forward with. That's how we basically move forward. The goal is essentially to hit that annual cadence. We basically look at a scenario where when we're coming up against the final iteration in node N minus one and the first iteration of N, whether we basically double drive those endpoints to make sure that we have a seamless coverage in terms of where one node reaches its apogee and another one starts its infancy.
Great. Next question. All right, over here to Stacy, please.
Thanks. I guess following up on those lines, I noticed on your charts your 14 nanometer plus-plus actually had performance that was higher than the initial 10 nanometer. Obviously, the 10 nanometer has lower power. If process density is so important, why wouldn't you be developing a higher performance 10 nanometer today? Presumably, that would be more cost-effective and have better traction in the marketplace. Is this a statement on where, for example, 10 nanometer yield
Let me at least start with that because I did show those 14 nanometer plots.
You did pick up then that, yes, the 14 nanometer is at a relatively constant capacitance, 10 starts lower. Again, as I showed those various performance curves, we can choose for different products where we want to lie on there. You don't necessarily have to be at lower performance because you can move around a bit.
Why would you wait until the 10 plus or the 10 plus-plus to actually get the performance of the 10 nanometer product out? Why would you wait to have the advantages of the density improvements? Because it looks like right now you're sticking with 14. Again, is that a statement on where yields are, or is there another driver of that?
Maybe I can let Kaizad answer, but I think you're adding on, we continue reinventing things, of course, we're going to come in and put those in as soon as we have them available, too. You have to go through waves of work to put together all the process innovations.
That's basically correct. There will be new features, new techniques added. They were done on 14 to go from 14 to 14 plus to 14 plus-plus. It didn't just happen automatically. There were experiments needed.
Yeah. It's work, right?
simulations needed.
Sure.
The same thing is true on 10.
That's why it doesn't all happen at once.
Howard.
I think it's also important to say.
Yeah
that I feel that on the product side, we don't have a knee in our back to push us towards 10 at a rate of knots until these guys are really comfortable, they've dotted the Is and crossed the Ts, because they're giving me a really good 14 plus-plus node in the meantime to keep my annual cadence. Again, I want to go and amplify that I don't necessarily think our core generations are going to be synchronized necessarily with process node evolutions. That may happen, it may not happen. What won't change is the fact that we're on an annual cadence with a predictable performance increment between nodes, and that's really how we're constructing our roadmap.
Howard.
Stacy, just to return to your original question. Depending on the type of product, the lower power can be a significant advantage and a reason to go to 10 over 14 plus or plus-plus. Depending on the attributes of the product, some products may prefer to be, if it's power unconstrained, may prefer to be on one option versus a more power-constrained product would want to be on another. If you have an architectural innovation that significantly adds to the transistor count and adds to the power, that would provide performance and may benefit from being on 10 versus 14. As Murthy is suggesting, each product is going to have its own optimal sweet spot
Yeah
of where it wants to land.
We're going to look at as they add transistors about where we place ourselves on those curves. Just back to the innovation thing one more time, because I do think that is so critical. Once we invent some new technology, we can understand ways to apply it to a lot of different nodes. We're not just going to stand still and say it only goes here. We're going to look at how we can best apply it.
Great. Let's come back over here.
John Pitzer with Credit Suisse. Kind of apologize for this question, I think almost every week there's speculation in the investment community about whether your 10 nanometer is hitting targets or getting pushed out. Can you talk a little bit and just level set us as to when we should expect to see 10 nanometer first production, and just how the ramp of Cannon Lake is going to progress as we exit 2017 and go into 2018?
Sure. As we said at Investor Day, we're still on a trajectory where we believe volume ramp will be in the first half of 2018. We'll be in production by the second half of 2017, and right now we're targeting shipment towards the end of the year. Whether it's this side of Christmas or the other side of Christmas is a little too close to call at this stage.
That's helpful. As a follow on, at Analyst Day, you talked about DCG ramping more quickly at leading-edge nodes. I guess, Mark and team, could you help me understand, because those have historically been larger die sizes and there's a cost penalty to ramping large die sizes on new nodes. Are you doing anything differently? Is this sort of the advantage of EMIB? I guess as you think about EMIB, how much can you deconstruct a chip before it starts to become an issue in the back-end packaging?
Mark, do you want to take that one?
Well, I'm not quite sure I caught the gist of the question. Was it whether we are going to start ramping 10 on a small die or a large die?
Well, the issue is if DCG is going to start taking more of the burden of leading-edge process technologies, they tend to be larger die within your product portfolio. If you're ramping larger die first, I'm assuming there's a pretty hefty cost penalty to do that. How are you trying to offset that, if I understand what you're trying to accomplish with DCG ramping more quickly on the leading-edge nodes?
Well, maybe I'll let Murthy firstly answer that question, how you see the strategy for the DCG products.
Yeah. Clearly, John, you picked on some of the key messages. To be the first or one of the first products on a new node, clearly you're constrained by a die size that needs to be sensibly hit in order to make sure that you're not exacerbating the issues of the defect density being quite high in the early periods. Therefore, the ability to go towards more of a disaggregated die construction helps in that regard. Therefore, if you look at, for example, the benefits of EMIB together with maybe die partitioning, then you can understand where maybe server can basically complement or be benefited from moving onto a new node first. You take a 600 square millimeter die, you think about a rational partitioning of that die into smaller tiles, and then using interconnect technologies such as EMIB to reconstitute a monolithic level of performance.
I think you can see how that all dials into server being able to take advantage of newer nodes quicker.
How much can you deconstruct a chip before it becomes a performance issue?
I wouldn't mind repeating that question for us.
How much can you deconstruct the chip actually before it becomes a performance issue?
I don't have a specific checklist there. Right now, I think what we're really looking at is really looking at individual tiles that probably wouldn't be too dissimilar from what you would see in a client size die and sticking those together. It's not like small die. They're still fairly major die, but they're clearly a lot smaller than our traditional server die.
Let me come over here to Tristan.
Hi, Tristan Silva. Just as a follow-up to John's question, what's the customer feedback as you move the next node to DCG, versus what you've done in the past? Also implication of 10 nanometer timing into the PC segment?
First of all, I run a lot of the engineering that supports the server business. I couldn't really represent what the customer feedback is. That's probably a question for Diane. In terms of the 10 nanometer question, again, let me repeat what I said to John. We're on a trajectory where we'll be in volume ramp by the first half of 2018. We'll be in internal production ramp by the second half of 2017. As I said, in terms of first shipments, whether it's before the end of the year or just after the beginning of the year, it's too close to call. I think it's still generally in line with the timing that we have aligned with our customers. We don't necessarily see any perturbation in launch plans today.
On the left side here.
Hi. Jerome from Exane BNP Paribas. What are your ambition in foundry? What kind of market share are you targeting among the $23 billion you mentioned? Are you going eventually to be a foundry for competitors?
I think specific ambitions, we haven't declared any beyond the fact that I think there are strategic partnerships and co-learning that could be available to us that could be mutually beneficial, both to the internal product business of Intel, as well as essentially providing a degree of extension of our foundry capability for other relationships. In terms of types of customers, I don't think we're setting ourselves up to be a general purpose foundry. We're really looking at strategic partnerships that essentially deliver win-win arrangements both for Intel and their customers, and a degree of technical cooperation that is part of that win-win story. Up in the front here.
Hi. I guess we've talked about or heard about your density and cost lead for several years now. Is there anything about these advances that you outlined today that specifically, are there any that stand out in your mind that will leverage into new product categories or improve market share in some categories that you guys have been targeting for some time but haven't gotten that level of traction yet?
Well, scale transistors, higher performance transistors, lower power transistors, lower cost break transistor, these are technology benefits that I think will benefit the whole range of product lines, from the very smallest mobile chips to the very largest server chips.
To add to that, what you heard today was not just an explication of Moore's Law, which is providing more and more transistors for the same number of dollars, which allows a broad range of products to benefit. You also heard about our 22FFL technology, which kind of takes our proven FinFET technology to address a new market segment where low leakage is extremely important. You also heard about the heterogeneous integration type technologies, including EMIB, that allow us to stitch different types of IPs together. I think the combination of all those things can and will lead to a broader segment of the market being addressed.
I think we've recognized for a couple of years now that from a process technology perspective, one size does not fit all. We're developing derivative versions of each technology, some tuned more towards a higher performance, others towards a lower power or SoC type applications. Now, maybe the more extreme example, 22FFL, really optimized for that market segment.
We do look at those. I do not know if you remember in the 14 nanometer update, I really walked through a whole list of features that we add to the, quote, "base technology," right? We can look at what makes most sense for any given product and work with the product teams to try to put up the right, call it flavor, that is going to make that segment successful. We are constantly looking at do we have the right technology portfolio to really build whatever we want to build.
Maybe to add to what Ruth said, exactly as Ruth said, actually, as we diversify the flavors of transistor technology and their optimization points in a node that is coming towards its end of its lifetime for our core products, it is then in a state where our other product portfolio can take benefit of it. As I said in my talk, a trend you will continue to see is as our cores move out of node N, a number of our other products, such as our modem technology, our networking technology, our FPGA technology, are going to be moving into that vacated node. I think there is going to be a real sense of virtuous reinforcement of the maturity of the node in which a core product portfolio exits is going to be pretty sophisticated for new products to come into and get the benefits of that learning.
I see that very much as being a symbiotic set of events that will repeat from node to node.
I will add that I have had the opportunity to visit with many of our foundry customers or potential foundry customers, where I hear their feedback on our process technologies, what could be different or better. It is helping me, helping the process team to better optimize our technologies, not only for some of these foundry customers, but for our own internal products as well.
Back to Detroit.
Thanks. Why not introduce a new architectural design sooner than Ice Lake, which is 2019? You guys used to do architectural redesign every two years. Now it's between Skylake and Ice Lake, it's going to be four years, if I'm mistaken. Architectural design redesign used to be independent of nodes, so why not introduce one sooner than later?
I think we need to be really precise about the expansiveness of terms like architecture. Sure, we can talk about new ways of interconnecting the various IP blocks within an SoC to get better performance. Let's be also clear that what we're also doing is upgrading key pieces of IP, such as CPU or GPU, looking at different configurations of clocks and memory bus access speed. When you look at the generation from sixth to seventh to eighth generation, and we're delivering double-digit increases in performance, that's a mixture of modification at the chip level construct, the improvement of IP, looking at the transistor process evolution, and creating a compound chemistry of that to actually give us that performance improvement.
At the end of the day, what really matters is that when you open the laptop of a machine or you fire up a server, that the experience you get in today's product is distinctively better than last year's product. That comes from a combined chemistry of all of that stuff. There isn't really a panacea where you basically move towards a complete new architecture that in and of itself is necessarily going to give you all of those gains. We see our product roadmap basically being a continuum of continuing to deliver predictable annual progress.
On that note, if I recall, a lot of the innovation that's ahead of you will come from integrating a lot of different IP blocks, right? In itself, some of which will require multi-chip packaging to your point, some of this could be on die, and hence the need for re-architecting the silicon block, the CPU block. Is that something that you feel is not needed for the next four years and you'll only need it 2019? Or is there something you guys are thinking about architecturally from an innovation standpoint, what Kaizad was referring to intercept some workloads that your customers are asking for?
I think there are certain attributes of our roadmap that I think are very much dialed into a 10 nanometer transistor specs that we basically believe makes sense to really be launched as that technology becomes more mature. That's really the thinking on the outer parts of our roadmap.
Back here to Eric.
Similar question. I guess when I think about EMIB and these tiles, if you will, historically, you guys have embedded a lot of accelerators, video codecs, floating point, all these, and embedded it into the Xeon CPU core that's monolithic today. When we think about an EMIB world with these discrete tiles, does that mean more emphasis on individual tiles as an accelerator connected to perhaps a more simplified CPU core? Just wondering if you could help us understand that.
Maybe I'll take that if any of you guys have input. First of all, let's be clear, I think EMIB is not a panacea. It's useful technology where it makes sense. For example, some of the accelerated technology we may in the future choose to envisage may not have a gate count that necessarily makes great use of EMIB, and therefore, you might as well just monolithically integrate it. On the other hand, you could see scenarios where, for example, in a situation where you're looking at really high-performance graphics, a really high-performance CPU, where the monolithic power profile would not necessarily be able to contain that architectural thermodynamic equilibrium, then maybe die partitioning via EMIB could be a good way of mastering the physics.
In that context, you could think about using different accelerator engines that may need to be mixed and matched as possibly being using something like EMIB. At the same time, it might just be better to do a monolithic integration if they're really tightly coupled with a CPU and have a fairly modest gate size.
This is where Murthy said at the beginning, we really do sit down and do a lot of product process co-optimization to figure that out. There's no one right answer for that question you just asked, because depending on the product need, depending on what we're doing, we have to figure out exactly the best combination to put that all together.
A standard MCP via substrate interconnect may be really good enough. It depends on what the data rate is of that accelerator. If it's multi-hundred gigabits a second, it's going to be different than if it's tens of gigabits per second.
Just to follow up on that, just taking a step back. When we think about your hyperscale customers, this isn't necessarily EMIB centric, but more just an architecture question for you, what gives you guys confidence over the long term within a hyperscale scale-out data center that having accelerators either on package, monolithic die or EMIB, choose your variant, connected to the host CPU long term is what the customers want? Could you just, in that world of scale-out hyperscale data center, what's the benefit of having that versus a separate discrete accelerator bank for things like virtualized pools of resources, things of that nature?
On that topic, I really don't think, again, there's one ubiquitous one-size-fits-all. I think you're going to see a range of workloads. I think you're going to see a range of workloads that are going to basically be quite suited to instruction set based acceleration on, for example, a standard Xeon server. There are going to be areas where customized ASICs make best sense because it's a highly predictable workload. You're going to see other areas where a GPGPU might make better sense because essentially it's a very clear workload, but maybe adaptable in some scenarios. Therefore, I think Intel strategy is very much towards being able to have an approach where we have diversity in the way we look towards technical solutions. It could be using ISA -based accelerators. It could be using a dedicated ASICs in certain scenarios. It could be using GPGPUs.
It could be using EMIB technology to have interconnect. It could be using MCP. It could be using monolithic integration. I think the benefit that Intel has is, we have a number of IP in our arsenal to be able to adapt to specific workloads. Therefore, we'll have a very case-specific answer to each of those questions.
Back over this side.
I'd just like to come back to the slide you show of the cost per transistor for the density times the price per square millimeter. What I don't understand in this is where is the yield assumption? If there is any yield assumption, how do you assume the yield at 7 nanometer node and 10 nanometer node? How do you know this yield?
The assumption is that eventually all of these technologies reach a high mature yield. That's really where that chart is based on.
One more piece of this was that Stacy did show the cost per mega transistor across technologies, and that did include yield in that slide. That really does show the continued improvement wrapped up of density and yield when he shows that progression across technology nodes.
To add to that, in Stacy's graph, it was also clear that if you looked at the first product, you didn't see the full benefit.
Yeah
For example, Ivy Bridge, as well as Broadwell, which are the first products which did not get the full cost per transistor benefit, both because in the early days, yields are not as good, as well as in the early days, you haven't ramped your factory network to get the wafer costs down as well. So in the first product, you don't see that benefit, but as you go through into the second and third wave products, the yields improve and you do realize the cost per transistor benefit.
Well, he also had that second slide, right? Because there was that slide that showed for a given die size, what it looked like. Then the subsequent slide also showed it as a cost item so that you could see when you actually wrap it up with the yield included that the cost was continuing to decrease. Maybe that wasn't clear in that slide, but it does include the yield portion of that.
The assumption is that eventually for every node, the yield going to be the same?
Yes, we get to mature yields.
Yeah, we get to mature yields.
If you look at 14 nanometer today, it's getting to pretty mature yield levels.
Yeah.
The difference between what we had at the end of 22 and what we have on 14 now doesn't change that cost per transistor picture very much.
Today, our 14 nanometer cost per transistor is well below our 22 nanometer-
That's right.
transistor.
Okay. Understood. Thanks.
Yeah, the cleanest way is that chart that Stacy showed that really shows you the overall, with everything included, and that takes into account die sizes and the like.
Back up front.
Hi. I wanted to go back to Eric's question and Murthy's, I guess, comment in response to that. If the idea is that Intel has a lot of IP and depending on what the workload is or depending on what the customer need is, Intel's going to be someone who can provide that tailored solution for what that is. I guess, is the idea that it's not about integration and about total cost of ownership being driven by monolithic die or by co-packaged processors or things like that, and we're in a world where you need to be best in class at the specific building blocks in order to compete in hyperscale specific. Does that make sense, what I'm asking?
Yeah. I think it really comes down to right now, workloads are so much in their nascency. They're so variable that as you look at how you would predict on what platform to launch them, you're really taking a very early bet in such a formative part of the workload formation. What I'm really saying is that, just for example, from my own experience, the first smartphones had the image, the gaming, and all the graphics done on the CPU. Eventually, they disaggregated into more workload-specific architectures when these use cases became steady state. Everybody wanted a camera, everybody wanted to watch video, everybody wanted to surf the web, everybody wanted to see playback video. That dictated how we invested in specific silicon.
I think when you look in the roadmap of the future for whether it be the data center or even the client devices, some of the workloads are still very much in an experimental, will this grab the end customer's attention or will that grab the end customer's attention? Will this stick? Will that stick? There's a lot of experimentation going on. To commit to specific ways of doing things right now is a little early and a little premature, and therefore, what we're really saying is we have a platform that allows a lot of experimentation, and when that experimentation gets towards steady state use cases, we can actually define an optimized silicon solution, whether it be in terms of power, performance, area, or cost. I think that's really what I was really trying to say.
In the back.
Hi. This is Stephen Chin from UBS. Murthy, I just had a follow-up question to a comment you made earlier about how Intel Custom Foundry is not aiming to be a general-purpose foundry. With that in mind, I was wondering if you could provide more insight from a margin profile standpoint, whether your ICF business, where that might fall longer term relative to Intel's current corporate operating margin structure or relative to the best-of-breed foundries out there.
Yeah. Murthy, would you like me to jump in there?
Absolutely.
Stephen, since we're in the quiet period, I think we'll pass on that question for now, but we're happy to follow up with you when we're outside of the quiet period. Thank you.
Just following up on same question again. Say one of your customers has made the bet longer term that this architectural, whatever architecture they will use for some of these emerging workloads is the right bet. You said that it's too early to make a long-term bet on these workloads because they are very nascent in their life cycle. If they're committed to that bet, two questions, why wouldn't you guys actually be foundry partners to them, even though it competes with your business in some ways? Then two, what would you do differently in order to make sure that you have that same architecture for their data center on a go-forward basis?
If we have a customer that has a very clear understanding and clear perspective on how they want to pursue their workload management, we'll clearly work with them, and define a solution that basically meets their requirements. I think if the precision of their need is clear and there's a dialogue in terms of a specific implementation that is necessary, I think it would be within our strategy of making sure we delight our customers to follow their direction and work with them accordingly, and that goes for any relationship beyond just the data center.
In other words, you would actually make the part to supply to them and also fab it for them?
Well, first of all, it's not my business.
Sure.
I couldn't speak on behalf of Diane, and I'm not sure whether she's even got that request. Maybe that's a question that you best target at her. I wouldn't want to answer on her behalf.
Just quick follow-up. I know it took a while to realign all of these different pieces together to finally get things moving at the same cadence. Do you think that all the work is now behind you to basically align the architecture, the microarchitecture, the manufacturing, the various IP blocks so that the future cadences on a go-forward happen at
In line with what customers want, or is there a little bit more work to be done there?
Is all the work done? No. Have we made good progress? Yes. The one thing that I think is really satisfying to me is I think we've got a real degree of philosophical and planning alignment between our process technology and our product roadmap. I spend as much time with these guys as I do with people in my product organization. What we're really talking about is looking at what these guys are recommending against what I need in the product roadmap, what my team says they need in the product roadmap, and having an aligned discussion of these are the rules of the game, annual cadence, predictable performance improvement, and being able to make sure that we have business that can rely on a contribution from our foundry and process that underpins their businesses.
I think the thing that I'm most pleased about is I think we've got a great deal of insight and an alignment on that plan. I'd let my other colleagues comment, but I think we've now really got a way of thinking that essentially unifies the company's thought process. Still a lot of work to do to go from intellectual alignment towards having all parts of our roadmap aligned on that theory. I think it's now on a path that I think is on kind of like an autonomous navigation vector.
To return to Murthy's earlier image, we have a quiver full of arrows.
Yeah.
We have to pick the right arrow for each-
Well, we really do a lot of work internally. Again, you've asked some specific questions about this or that, but that is a lot of the things we can do internally, is really work in with each specific team to understand what we can bring to them.
We come back to the middle.
Thanks, Mark. Mark, I wanted to go back to a question I asked you kind of offline about EUV. ASML lithography's done a great job with the investment community, kind of convincing all of us that the sun sort of rises and sets in the litho bay. I'm kind of curious because the next development that's going to happen most likely is that TSMC and Samsung will be using EUV in their logic manufacturing, probably before Intel. How does that change the competitive dynamic when that happens, and if it doesn't really change it, can you just kind of dumb it down for us and help us understand why they going to EUV more quickly than Intel really doesn't change that lead?
Okay. First I'll say that EUV is a great technology for delivering improved patterning capabilities. You can certainly print smaller patterns with better fidelity with a single EUV exposure than you can with maybe two or three immersion steps. Today we can't commit to EUV because the manufacturing readiness, the manufacturing maturity of the tool is just not there. The uptime of the tool isn't yet very good. Number of wafers per hour through the tool isn't very good. If we made a public announcement today, "Yeah, we're committing to EUV," that would be a pretty hollow announcement. May sound good for a day or a week, but then you got to ship wafers. If the tool's not quite manufacturing ready, you'll suffer.
Let me also add that I don't think anybody is ahead of Intel in terms of understanding what it will take to get EUV into manufacturing. It's not precluded from being used on our 7 nanometer technology, because I've stated in public before, although we are initially developing our 7 nanometer technology on an all immersion flow, the design rules are set such that we can put EUV into certain steps, replace two or three immersion layers with EUV for a cost saving. We see EUV eventually as a cost savings.
That's helpful. Maybe as a follow-up, since the days that Andy was CFO, it's kind of been drilled into all of our heads that if Intel could move faster down Moore's Law, you would, the economics make sense. I'm just kind of curious, given all the optimization that you've been able to do on 14 and 10, and Murthy, given how the market sort of changed from this monolithic PC world into something that's much more heterogeneous around SoCs, is moving down Moore's Law as fast as you can still the best economic outcome for Intel? Or is what's happening now with the elongation of Moore's Law, as long as you can keep that competitive lead, actually a better economic outcome for the company?
Yeah. Again, I think it's a set of concurrent strategies that essentially at a business level, we can kind of cut through and exploit in cross-section. We have to drive Moore's Law as fast as possible. We also have to accept that that's a process of a great deal of innovation, and therefore, with a great deal of innovation comes a degree of proximity and timing. One thing that's really clear is that the fundamental point of Moore's Law is to get towards an economic equation, and you don't want to forestall that achievement of an exemplary economic equation because you're kind of like wanting to shave six or 12 months off the schedule.
In order to protect that economic path and still achieve that economic rate that we talked about, we evolve our current processes to take a little bit of air cover to give us that sense of ability to optimize. I'm not compromising my desire to have an annual cadence on my product portfolio Because I've got a make-before-break connection between node N minus one and node N. For me, I think it's a much more sophisticated discussion today. One, because we have a much broader portfolio of products than maybe when Andy made that statement. Two, Moore's Law importance is ever present for Intel.
What we're also trying to do is get towards the ability to drive all of our business towards a predictable cadence, which means we need to make sure that we cover some of that innovation risk with the ability to make sure that we can have agility in which node we can land a particular part. Our roadmap seems seamless to the outside world.
Now, let me expand upon that answer. As we run as fast as we can down the Moore's Law path, we do not forget to look to our sides as we do so and think and ask ourselves, are there other ways we can optimize these technologies, do derivative versions, to meet a broader range of products? Again, the main driver is to pursue Moore's Law, but we also look to our sides and look to ways to develop derivative technologies for a broader range of products.
In a nutshell, more and more.
All right. I think we have got time for a couple of more questions.
Thanks. There's been some speculation in the press recently that some of your competitors are exploring a gate-all-around technology, ideally for commercialization next year. What are your thoughts on that?
We are exploring a broad range of transistor options in our research and development groups, including gate-all-around. As much as we might like to use an attractive name like that, we make choices based on real hard engineering data, density, performance, and power.
Got it. If, this is Samsung supposedly, if Samsung actually develops something that is gate-all-around next year, where does that put you potentially in terms of your roadmap?
I think still with a better technology.
On power performance scenario?
Yeah.
Okay.
All right. For our last question, why don't we come here to Tristan?
You talked about 14 nanometer FPGAs being in production now. Fair to say that there was some initial delays at the time when Altera was a standalone company. Looks like Xilinx is going to access seven nanometer from TSMC, so we know not an apple-to-apple process with what you're doing, sometime in 2018. Is the plan to accelerate the node migration in FPGAs going forward, do you think that you now have ways to do that, or how should we look at the next node for FPGAs?
I think we're open-minded. I think at the end of the day, what we're really looking at, is what is the best technology or profile of IP that lends itself towards being the first to ramp a node. We've talked about technical enablement that has allowed us to reconsider whether a server, for example, should be looking at one of those areas. There's nothing to preclude that discussion encompassing the broad spectrum of Intel's technology. We may consider whether, in the future, FPGAs may make a better sense. Clearly for us, as I said in my talk, all of our product portfolios will ultimately benefit from our transition from node to node. As I said, when we exit 14 on our core roadmap, FPGAs moves into 14 in mainstream.
I wouldn't discount options in the future where we may rethink whether FPGA is the right technology to ramp a particular node structure with. We're looking to make sure that we provide our FPGA business with a process that is aligned with the competitive advantage it wants to generate in the market. If they believe that in the future, there comes a time where they need to be on a leading node, I see no reason to preclude that from our judgment.
Let me just add that the fact that there's so much debate and so much clamor to be first on a node simply makes the point that Moore's Law is alive and well.
All right. Thank you all for joining us. With that, we'll wrap up the webcast, and we appreciate you spending the day with us.