Tokyo Electron Limited (TYO:8035)

Investor Day 2021

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Oct 12, 2021

Now it's time for us to start Tokyo Electron IR Day. Thank you very much for joining us today despite your busy schedule. I am Yatsuda of IR Department acting as a moderator in today's session. It is the second time that Tokyo Electron holds IR Day. Last time, we organized IR Day to present our revised midterm environmental goals, newly released programs and our help of digital transformation, which moved to a new location. Today, we hold IR Day as we find it as a good timing after publishing our first integrated report in August year. We will present various activities related to ESG value chain and corporate value creation. We would appreciate it if you could kindly understand that we cannot talk anything about the current financial performance in this IR day since it is before the second quarter financial announcement. Now let me introduce the eight attendees on our side. Mr. Tetsuo Tsuneishi, Corporate Director Chairman of the Board. I am Tsuneishi. Thank you very much for joining us today. We're very happy to see so many people joining in this IR Day. We're going have three hour session, very long session. Really appreciate this opportunity. We'd like to share our idea and our basic strategy, including ESG. With focus on ESG, we'd like to talk what we value and how we promote and contribute our growth and the contribution to the society. And also, we'd like to talk about the semiconductor technology innovation in the future and our strategy product strategy. So there are so much items we want to share taking this opportunity. So I hope today's meeting will be fruitful for all the people who join us today. COMPANY Next, Mr. Toshiki Kawaii, Representative Director, President and CEO. I am Kawaii. Thank you very much for participating in this session despite your very busy schedule. Next, Mr. Yoshikazuno no Kawaii, Corporate Director, Executive Finance Vice President, General Manager, Global Business Platform Division, Finance Unit. I am Noonokawa. Thank you very much. Next, Mr. Keiichi Akiyama, Vice President and General Manager, CTSBS Business Unit. Ayama Kiyama. Thank you very much. Today, I try to talk about leading HEUV Technology, relevant technologies later. Next, Mr. Isamu Wakui, Vice President and General Manager, ES Business Unit. Next, Mr. Hiroshi Ishida, Vice President and General Manager, TFF Business Unit. I am Ishida. Today, I'd like to present the film deposition new approach on behalf of TFFPU. Next, Ms. Sumire Segawa, Vice Division General Manager, Corporate Innovation Division. I am Segawa. Thank you very much for joining us today and Doctor. Akihi Sasekeguchi, Deputy General Manager, Corporate Innovation Division. I am Seigawa. Later, I'd like to talk about the technology trends and business opportunity for our company. Before starting the presentation, let me explain the flow of today's meeting. The agenda today's meeting is shown on the slide. We will have two hour presentation session, including ten minute break in the middle. After all presentations, we'll have question and answer session. We plan to close this meeting at 05:30 Japan time. This meeting uses two channels on Webex, providing simultaneous interpretation between Japanese and English. As we explained in our e mail, you are kindly requested to use apps on PCs or mobile terminals if you plan to ask questions. But if you are not going to ask question, you can use telephones. Since this is a meeting for institutional investors and analysts, we appreciate your understanding that we receive questions only from institutional investors and analysts as usual. We'll upload the audio contents of this meeting, both in Japanese and English later. We are happy if you also refer to them. Now Mr. Kawaii, CEO, will present aiming at global excellent company, talking about our major initiatives for value creation and value chain. Good afternoon. I am Kawaii of Tokyo Electron. Thank you very much for joining us in our IR Day today despite your busy schedule. Like last year, due to the COVID-nineteen spread, we hold this IR day as an online meeting. But I'm very delighted to talk with you in this opportunity. Along with the shift to data driven society and to decarbonation society, the semiconductor devices become increasingly important. And accordingly, our company is expected to exercise more and more important roles and responsibilities. The title of my presentation today is Aiming for Global Excellent Company. I'd like to present the business environment and our major initiatives. When I look back the situation of the word from last year to this year, we have been struggling with the global spread of the COVID-nineteen infection and a number of natural disasters in climate, such as torrential rains in Japan, hurricanes and cold waves in North America and wildfires. There have been various issues globally, including geopolitical issues like trade frictions and human rights issues, which have had considerable impacts on our society and our daily life. In parallel, digital transformation proceeded in our life and every industry last year, which highlighted the significance of the semiconductor devices essential for ICT. The transition to the data driven society is progressing at an unprecedented speed. And also we need to address the global environmental problems. Amid those circumstances, the tidal wave of digital and green is spreading across the world. What I mean by green here is carbon neutral aiming at decarbonization to suppress CO2 emissions. In order to build a strong and resilient society in which economic activities are not disrupted in any situations, the world is implementing ICT and digital transformation and striving to realize a decarbonized society. In the future, digitalization in every industry, such as autonomous driving, smart city, smart factory, smart agriculture and smart medicine is expected to spread widely through the society. And it is semiconductor devices that supports all of these at their bedrock. The semiconductor devices used to be dubbed as rice of the industry in Japan, meaning the essential building block of the industry. Now as an essential building block of the industry, society and our life, it is playing wide ranging roles. In the past, the semiconductor market was driven by products, mainly by electronic devices such as PC and smartphone. At present, various services using data, in other words, value that people want to realize are the main drivers. It is about seventy years since the transistor was invented in 1947. The global semiconductor market was about $440,000,000,000 in 2020. And the market size is expected to reach about $1,000,000,000,000 in 02/1930. This means the market will be more than doubled in size in the next decades. In ten years' time, we will see another market of the equal to the current market in size. Accordingly, WFE market size is expected to exceed $90,000,000,000 in 2021, but it is just the beginning. Electric vehicle, fuel cell vehicle and autonomous driving will be spreading. In addition, five gs will be widely adopted. In parallel, post five gs development will be proceeding. To realize ICT digital transformation and decarbonization, the semiconductor is required to have more storage, faster speed and higher reliability with lower power consumption. Accordingly, the WFE market will grow furthermore. This slide shows the trend of the fee market that our company analyzes. The blue on the left represents the past, while the green on the right represents the future. As you know, in the past, semiconductor market growth was driven by emergence of new models of PC and mobile phones. Therefore, once their supply got stabilized, the demand for semiconductor devices slowed down, which was called silicon cycle. The arrival of data driven society together with IoT, however, triggers an explosive increase of the semiconductor demand. Continuous capital investment to leading edge semiconductor devices supporting value driven consumption is essential. The IC manufacturers having high market share are strongly aware of supply demand balance. Based on these factors, we believe the WFE market has entered a new phase in which it will grow strongly in a staircase shape. As I said so far, due to high expectation to the semiconductor and WFE market, Tokyo Electron is expected to exercise more and more roles and responsibilities toward the future. As our corporate purpose, Tokyo Electron implements our corporate philosophy. We strive to contribute to the development of dreams inspiring society through our leading edge technologies and reliable service and support. Specifically, the implementation of the corporate philosophy means that by leveraging the expertise of the process tool manufacturer, we will make an effective use of all resources, including the employees who are the source of value creation, contribute to both digitalization and greening through the semiconductor technology innovation to expand the longer term profit, enhance corporate value continuously and make all people around our company happy. Based on this concept, we published our integrated report in August. Today, I will touch upon our efforts for value creation. That is one of the topics presented in this integrated report. To expand the longer term profit and enhance corporate value continuously, we have defined our majority. Based on the management foundation, including safety, quality, governance, compliance and risk management, our majority is composed of product competitiveness, customer responsiveness and higher productivity. To intensify this materiality, we will implement the strategy, making the maximum use of our expertise and strength. Our strengths are shown here. One and only WF manufacturer offering process tools essential for the advanced device patterning technologies. Our share in these products ranks number one or number two in the world. In particular, we maintain 100% share in quota developer for EUV lithography, which is essential for the leading edge device nodes. We have the world's largest installed base of about 78,000 units, which increases by 4,000 units every year. Based on this, we have built a field solution business model. Based on these strengths, we will keep a productive R and D investment to create innovative technologies leading the world. By aligning technology roadmap of multiple generations with the customers and supporting their manufacturing lines of the current device nodes, where we'll develop products with high success probability and create unique high value added technologies that only TEL can develop to support digital and green. For manufacturing aspect as well, we have been building our infrastructure. In 2020, the new production building started operation in Tohoku plant and Yamanashi plant. And in May, we announced that we acquired the land in Miyagi plant, where we'll support the stable supply to address rapidly growing semiconductor demand. Toward the sustained growth of our business activities, we are building resilient supply chain based on the solid relationship of trust with our partner companies. For our partners, we perform STQA, supplier total quality assessment. In addition, every year, we conduct CSR, BCP and survey on conflict minerals and environmental laws and regulations to promote the supply chain management. In addition, we have established Miyagi Technology Innovation Center last month, aiming at merging diversified technologies of our suppliers to create new innovation. We will keep working on sustained growth of the industry through collaboration with the partner companies. Next, I will talk about our sustainability efforts, including the ESG initiatives in our value chain. To contribute the development of international community, we are promoting the sustainability efforts through our business operation. We have linked the United Nations SDGs and our corporate materiality. We carry out group wide activities and also participate in international initiatives. Along with their framework, we analyze impacts on our opportunity of our business and disclose relevant information. Our activities are highly recognized across the world. We have been selected on the list of global leading ESG investment indices. We will make a continuous effort so that we can win trust from our stakeholders. We are working on reduction of CO2 emissions The first perspective is to contribute to enhance per watt performance and reduce power consumption of semiconductor devices through our semiconductor manufacturing technologies. The second is energy conservation of our products and business activities. Toward the midterm environmental goals of 02/1930, one of the most demanding goals in the industry, we will strive for decarbonization For 70% reduction at our sites, we mainly work on 100% renewable energy use. Yamanashi and Miyagi plants have already switched to renewable energies at 100%. Kumamoto and Iwate plants plan to switch next year. The third is the e commerce initiative that we announced in June. This is a new initiative to build sustainable supply chain and promote global environmental conservation activities throughout the supply chain. Next, I will talk about our efforts for safety, in particular incident. This figure shows TCIR total case incident rate per two hundred thousand working hours. The dotted lines represent the average of material vendors, IC vendors and tool vendors. The solid lines indicate the value of IC vendors A and B and those of competitors, C and D as well as our own values. As you can see, our company fits in world class safety. While expanding the business size, we maintain high level of safety. What we aim at, however, is zero incident. Under the banner of safety first, we will make every effort to improve safety in every business activity of our company. It is our employees that perform all of our business activities and realize our sustained growth. It is people that drives the company, employees are the source of value creation. Based on that idea, we focus on the three things. First of all, code of conducts, which is based on the corporate culture we have committed ever since our foundation. We call it tail value to be shared with our employees. The second is motivation based management. Employees' performance is determined by their ability and motivation. They were screened by ability when they entered the company. Motivation is critical to raise their performance. To enhance their motivation, it's important that they have dreams and expectations for the future of the company. They have an opportunity to challenge without fear based on strong financial basis. They are fairly evaluated and recognized with globally competitive reward, and they can communicate openly. We are taking various measures to enhance the employee engagement, such as introduction of new HR system designed to facilitate dialogue between supervisors and subordinates. The third is diversity and inclusion. Focusing on perspective three gs, namely global, generation and gender. We will announce specific goals this year to reflect them in the corporate governance guideline. This Slide shows the code of conduct, tail value that I talked about. Pride, challenge, ownership, teamwork and awareness. You can see the idea of each of five. In challenge, for example, it states we will be generous for failure and highlight importance to learn from its process and result. This represents our basic idea Intel. Fiscal year 60 starts in April 2022. Based on value, we will explore a new era to keep being dream inspiring and vivid company. At present, we are operating 76 sites in 18 countries throughout the world. Looking at the customers' future investment plan, however, we expect our sites, employees and suppliers will further increase. We are determined to be highly aware of human right, including employment conditions, work environment and occupational health and safety throughout our supply chain and contribute to development of dream inspiring society. To increase our longer term profit and enhance our corporate value, we set the goals of operating margin and ROE in the midterm management plan, which is our offense management strategy. In parallel, we are committed to safety, quality, compliance, employee engagement, risk assessment and security. These activities essential for our business sustainability, our defense strategy and at the same time, it's our strength. Each one of the employees will work on these to further strengthen our management foundation. Aferent future, the semiconductor device realize ever evolving semiconductor device. The WFE market supporting semiconductor device is now in the further growth phase. The corporate growth is driven by people. The employees are the source of value creation. Tokyo Electron will implement the corporate philosophy, leverage our expertise and diversified resources, create innovative high value added technologies that only TEL can create and provide these technologies to the society. We will keep challenging and evolving from now on. And we aim at true global excellent company strongly trusted by all these stakeholders. Thank you very much for your kind attention. Next, Ms. Segawa, Vice Division General Manager, will present supply chain initiatives for the environment. I am Segawa, Vice Division General Manager of Corporate Innovation Division. I will present eCompass, our supply chain initiative designed to enhance the environmental conservation efforts. On 06/16/2021, we announced initiation of eCompass, the supply chain initiative focusing on the environment. ECompass is an abbreviation of environmental co creation by material process and subcomponent solutions. E Compass also represent environment compass. We want to make this initiative a real compass leading our community. The logo shown in this slide expresses our resolution toward this initiative. CEO of Compass uses a symbol of infinity, expressing sustainable use of resources and energy and permanent relationship with our stakeholders. The color gradation from blue to green represents our future journey toward environmental footprint reduction through co creation with our partners. This is one of the important initiative in pursuing our corporate philosophy to realize digital and green society that Kawaii san said earlier. I will present the three underlying factors of this new initiative foundation. The first one is climate change. As you know, over the past few years, unprecedented massive disaster took place in many parts of the world. Climate change induced by global warming is one of the factors to cause these disasters. The international community is raising awareness of environmental issues regarding them as intimate crisis for us. As all business across the world are expected to address the environmental issues, the IT industry is no exception. Our customers, namely IC manufacturers, become increasingly aware of the environment. Tokyo Electron is a global citizen doing business on this planet, is determined to be responsible for building the supply chain with high level of awareness of the impacts on climate change. The second factor is an increasing trend of international treaties and legal requirements for the environment. This figure shows that international treaties, laws and regulations for the environment have been increasing year by year, which is on the horizontal axis. Some of these legal requirements have significant impact on business activities. In order to prevent the legal requirements from becoming our business risks, we need to assess the future trend and take proactive approach. An effort to minimize business risk in the entire supplier chain will become increasingly important. This slide shows the third factor. Now that the semiconductor industry becomes essential in the society, Tokyo Electron must take responsibility as a company aiming at the global excellent company and take leadership in achieving sustainability in the entire industry. We deliver our products to IC manufacturers to help them realize leading edge devices, featuring high performance and low power consumption. As IC devices manufactured by applying our leading edge manufacturing technologies are widely used in the society, they will contribute to reduction of environmental impacts for years to come. Doctor. Seki Guchi will present the details of reduction of environmental impacts through our manufacturing technologies. Our business activities to pursue both digital and green are supported by the alliance with many partners. In order to raise awareness of the environment together with the partners, we launched eCompass as a supply chain initiative focusing on the environment. This shows mission, vision and value of eCompass. The mission is that we will promote green performance enhancement of microelectronic industry through supply chain wide collaboration to reduce global environmental impacts. The vision is that we will work on the green technologies in the entire supply chain to co create sustainable and affluent future where humans and the nature coexist. The value is that we will provide high green performance microelectronics manufacturing technologies and process tool technologies, address legal, regulatory requirements and reduce environmental footprints in our operations under this mission and vision. By implementing the mission, vision and value of eCompass through our business activities, TEAL will make use of all resources to realize both digitalization and greening in the society. By promoting our active environmental initiative, we will pursue our corporate philosophy. We strive to contribute to the development of dream inspiring society through our leading edge technologies and reliable service and support. Next, let me talk about specific Encompass activities. There are three major pillars. The first one is to pursue sustainability in the entire industry through enhancement of partnership. The second one is to provide environmentally conscious products by realizing process tools free from environmentally hazardous materials. And third one is to accelerate innovation of manufacturing technology by proactively developing green technologies. We will work on these activities to promote environmental impact reduction and green technology innovation in the entire supply chain. Next, I will talk about what we are doing in these three activities. The first activity is enhancement of partnership. This Slide shows CO2 emissions in the entire value chain of our company. In comparison with CO2 emissions of TEL itself, which is 186,000 tonnes, the CO2 emissions in Scope three, which covers upstream and downstream of supply chain, is more significant. The CO2 emissions in downstream, in particular, attributed mainly to use of our products, enhancing environmental performance of our product directly lead to the reduction of the environmental impacts of entire semiconductor industry. We will encourage our partners to understand the mission of eCompass to enhance green performance of microelectronics industry and strive to establish solid partnership. This shows examples reduction of environmental impact in procurement distribution. The example on the left is model shift between the suppliers in Western Japan and our Kyushu and Miyagi sites. Truck transportation has been replaced by railroad transportation to reduce CO2 emissions. From this fiscal year, model shift effort will be expanded to the suppliers in Kyushu so that we can further reduce CO2 emissions. The example on the right is introduction of returnable packages and containers such as plastic trays and innovation of packaging materials to reduce consumption of aircaps and disposable carton boxes. In the upstream of our value chain, each one of these activities may look insignificant, but we will review each business activity and accumulate small improvement little by little so that we will raise awareness among ourselves and our partners. The second activity is to develop process tool free from environmentally hazardous substances. Our process tools are composed of parts manufactured by many partners. To be delivered to our customers. We believe it is important to build supply chain pursuing minimization of environmental impacts since the environmental regulations are rapidly increasing. By enhancing the alliance with our partners, we'll be able to eliminate substances of environmental concern from the component we purchase and provide environmentally friendly products to our customers so that customers can use our products for years with peace of mind. We can build the solid relationship of trust, not only with the customers, but also with all stakeholders and eventually enhance our corporate value. Now let me show you some specifics. As a first step, we will learn from Europe and The United States, which are advanced in environmental initiative, proactively identify substances of concern for negative impacts on environment and human body and share information with the partners. For the substances of very high concern, we will proactively find alternatives and develop a method to minimize their release to the environment. Joint technology innovation with partners may be very useful for us. The third activity, the last one is to develop the green technologies proactively. The traditional product specifications were composed of hardware and process performance specifications and operation safety specifications. We will add environmental specifications to accelerate development green technologies for our best products and best technical services. The green technologies will serve as our competitive edge to facilitate the technology innovation. Use of energy, water and chemicals require drastic technology innovation. We will enhance the alliance with our partners so that we can propose attractive solutions leading to reduction of environmental impacts. Every site of TEL has accelerated development of green technologies. Let me present an open innovation together with the partners. This is Miyagi Technology Innovation Center, whose construction was completed on 09/22/2021. This center was built to enhance development of innovative manufacturing technologies at Tel Miyagi, which manufactures etching systems. The center leads the development to drastically improve performance, quality and lead time of our products and it also have enough area and open innovation areas where we can use for the collaboration development. Making active use of this co creation area, where we'll promote development of green technologies in the eCompass initiative. So in my presentation, I presented our activities of eCompass initiative. To implement the value of eCompass, that is, we will provide high green performance microelectronics manufacturing technologies and process tool technologies, address legal and regulatory requirements and reduce environmental footprints in our operations. We will explore new partners and seize technologies in the world to facilitate the activities. Really appreciate your continuous support. Thank you very much for your kind attention. Next, Doctor. Seki Uchi, Deputy General Manager will present technology trends and tells business opportunities. Thank you very much, Yasuda san. I'm Seki Gucci, Deputy General Manager of Corporate Innovation Division. I will talk about technology trends and Tails business opportunities. This is today's agenda. Firstly, I will talk about the recent market trends. Then I will share my ideas about how these market needs will impact development semiconductor devices and how logic memory seamless image sensor and other leading devices will evolve. And finally, I will present the direction of our development activities and future needs. Before getting into the complicated topics, however, let me warm up a little bit. I use these two photographs quite often in the conferences recently. On the right, you can see Ford Motor T, a car more than one century ago. It was manufactured in an innovative process of low cost, high volume production. It features 20 horsepowers, maximum speed was about 70 kilometer per hour. It is quite fast, but in terms of safety, the Model T is far behind the autonomous driving vehicle, which uses numerous sensors to bring its passengers safely without any stress to their destination. The autonomous driving vehicle is a kind of collection of semiconductor technologies. However, Ford didn't have one unique feature that even supercar on the left cannot match. That is, it can operate and can be made without any semiconductor devices. But what I want to highlight here is not about the restriction due to the tight supply of semiconductor devices, but about the automobiles have grown platform to drive the semiconductor industry, although it took some time so far. Some more information, I'm sorry, let me add some more. Semiconductor ratio was mounted to Chevrolet model At that time, price of the car was $850 while the radio was $200 Electric vehicle was originally invented in 1830. Its share grew gradually until 1870, but it was driven out of the market by cheap Model T. I sense something in common with semiconductor technology in this story, such as technology innovation and cost reduction. At present, semiconductor device is essential for a car, logic, memory, sensor, communication and display various semiconductor devices are mounted on a car. An instantaneous decision made by AI on each side, which is essential for autonomous driving. Building communication infrastructure to send data collected by sensor through high speed network is also essential. The cloud computing infrastructure, which efficiently process the data, are evolving by using various innovative accelerators. AI accelerator, quantum accelerator are featured in the media, but they are not free from programs. The server FAM shown on the right, which looks a little bit untidy, have many problems. Increasing power consumption, heat dissipation, delay taking place every time data are transferred, there are so much room for improvement. But this is why there is no end in the research activities. Now that a car is equipped with leading edge technology node devices for logic and memory, the car is driving the semiconductor industry as one of the launching platform of the semiconductor technology. Machine and devices generate huge amount of information. The same applies to mobile devices, which has been driving the industry so far. People full of wearable devices, in a sense is also a platform for the technology. Health monitoring is a promising category to grow in the future. Hobbies are also important, so they are not essential. Biologic, such as Internet of cats, may generate more data than people in some areas where people like PET. How do these market needs impact the semiconductor device development? This shows our corporate technology vision. I have shown this before several times. The arrow in the middle represent continuation of Moore's Law. The arrow indicating main device evolution is very healthy. The green arrow indicates customization, while the purple arrows represent hyper mass. In other words, the purple represents the needs of productivity enhancement or continuation of legacy nodes. The blue in the middle represents device scaling, three d device structure and new material development. The green represents SDTCO, namely system device technology and new architecture. The system integration supporting device hybridization is part of this green arrow. Next, I will present more about the system integration. For system integration, there are four different categories. From the left, logic, memory, back end of line and other options such as phoning. I'll go one by one. First, logic. You can see two d shrink as an extension of device scaling, new structure and DTCL to co optimize device design and process technology. This shows memory. Here again, two d shrink, more stacking for storage enhancement and three d DRAM to break through the planner device shrink. The third one, this is back end of line interconnect process. To reduce data transfer delay, a new technology to embed memory and accelerator on chip instead of off chip is in progress. As many of next generation memories can be embedded to interconnect structure, technologies to various memory structures to back end applying is being developed now. NPU or Neural Processing Unit is developed to make device have multiple functions. In addition to the conventional SoC with CPU and GPU embedded, We can also see SoC with NPU dedicated to machine learning embedded. Number four, this shows heterogeneous integration, which is driven by evolution of bonders. I'll talk about it later on in my presentation. We must not forget SDGs, Sustainable Development Goals initiated by the United Nation. Tokyo Electron is working mainly on seven items. Our contribution is not limited to our own premises or products. This is the information we borrow from IMEC, a Belgium consortia and our development partner. On the left, the vertical axis shows the normalized environmental KPI, while the horizontal axis shows logic technology node. Energy cost and water consumption in the logic production are plotted here. Leading edge logic feature the lowest environmental impacts. The environmental impacts per device when it's produced by using leading edge technology is lowest, and our process tools are essential for the production of leading edge devices. I'll talk about this issue later in GAA. Now I will talk about details of development of major devices. So direction of the development of semiconductor devices. You can see important message under each device. The logic, the scaling with its structure change for cost reduction per transistor, lower power and faster device. NAND, higher stacking to reduce cost per bit. DRAM, scaling and new structure will enable reduction of cost per bit, lower power and faster device. And CIS CMOS image sensor, increase of pigments by scaling, faster speed, high image quality driven by new structure and materials. Now let me talk about trend and business opportunities of Logic device. On the right, you can see smartphone CPU evolution from 2014 to 2020. Over the past five generations, the number of transistors has been increased 6x using the same die size and the number of cores has been tripled. And now you can see brand new 16 NPUs as well. Memory cache size has been increased by about 6x due to evolution of structure, material and patterning technologies, so well integration and function improved drastically. Similarly, GPU performance has dramatically improved at the same time. There was another option to reduce number of transistors to reduce chip area. But in the case of HPC, priority was placed on improvement of PPHE performance. Scaling is essential to increase the level of integration. The key enabler is the patterning using EUV lithography and gap fill technology. For the final patterns, etching technologies with high selectivity suitable for various materials and dry technology to prevent pattern collapse. So these are very important technologies. What is essential to realize DTCO is various etching technologies with high selectivity and dielectric film and metallic film deposition technologies. This shows the logic roadmap from N7 node to N0.7 from left to right, showing major device parameters. When PP Polypitch times NP Metal Pitch are compared, integration will increase by a factor of 5.7. If DTC or cell height is included, integration per unit volume will be 23x. To increase integration that much, we need to develop GAA, the gate all around the new device structure. The GAA is also called Nanosheet. The vertical fin channel is placed horizontally to be made in a state of sheet to increase the number of stacking layers to meet performance specifications. A major characteristic is that fin width, one of the critical dimensions determined by pattern in the case of fin device, will be replaced by sheet thickness determined by silicon epitaxial growth. A large number of our technologies are used for formation of GAA, the core of the device. I'll talk about it later on The major modules for the GAA formation are shown on the right hand side, starting with MoldStack and H, next formation of inner spacer, followed by Nanosheet release. And after that, we'll see the replacement gate process. This is what we borrowed from IBM Research in New York State, one of our development partners. The cross section of two nanometer gate all around technology. You can see very good nanometer profile. This GAA requires advanced process technologies to make. The GAA device fabrication process is divided into four process modules. Number one, from the left to right, the first one is more stack and etch. STI, shadow change, isolation and silicon sequence GNM stacking layer are epitaxially grown. The second is Inner Space Module. This includes recess processing to control device characteristics and space formation spacer formation. The third is nanosheat release module. Depending on device time, silicon or silicon germanium layer is removed. This requires high selectivity etching process. And the last one is replacement gate module to fabricate gate electrode. Here, firm deposition and etching technologies play an important role. Here are actual examples, but because of time limitation, let me just skip this Slide. This shows patterning technology used in EUV, which is also essential for GAA device. As you know, EUV lithography features high resolution due to its short wavelength. Compared with ARRF, however, the number of EUV photons per dose is limited to onefourteen. As EUV features lower photon absorption reaction rate than ARF, EUV allows stochastic noise generation, which makes pattern rougher. Our company succeeded to reduce the roughness by co optimizing conditions of exposure and etching. What we need is global development sites. There are limited source or routes that we can get EUV exposed wafers. By collaborating with European, American consortia and our customers, Tokyo Electron is promoting advanced process technology development. This shows the deliverables of the collaboration. Could you follow the CDSM images from left to right? Originally, this nano pattern featured critical dimension of 14.7 and line edge roughness of 2.25. The CD was reduced to half and line edge roughness has been also improved, 1.5 nanometer by using our technologies. In the previous slides, I presented next generation GAA logic. Next, I'll talk about two generations ahead, stacking of GAA structure. This is CFET structure shown on the right, and bonding technology is a key. Bonders have been widely used for CMOS image sensors. For logic, it's used to fabricate backside PDN. Today, unfortunately, because of the time limitation, I cannot give you any details. If you are interested in, please let us know to our 3DI group. Now I take so much time for logic. I'd like to talk about memory and CMOS image sensor. As shown here, DRAM is full of high aspect ratio structures. Degree of freedom on the XY axis is very much limited. Pitch scaling is very difficult. Therefore, common shrink and scaling are very difficult. However, there have been evolutions over the past six years. From 2014 to 2020, data rate has been tripled and capacity has been raised by about 5x. Packaging technology with logic has evolved as well. Combining with GPU, DRAM can be dramatically increased amount of data that GPU can process at a time by using silicon interposer technology. As you can see from this roadmap of DRAM, DRAM changes milder compared with logic. Recently, three d DRAM development has been getting active recently. It's too early to present the details, but previously capacitor structure was vertical. The capacitor is placed now horizontally to be stacked. So that's how it's changed. As you can see here, we are developing processes required for formation of stacks, capacitor, cell transistor and wet line and bit line. I'm getting close to the end of my presentation. NAND integration can be enhanced by increasing the number of stacking layers. Device footprint can be reduced by putting logic cell under memory array. Techniques using monolithic and bonding tool have been established. This shows the NAND technology roadmap. From left to right, year by year, the number of layers per stack keeps increasing. The number of tiers also show a mild increase. Materials for white line are expected to change in the future. Challenges for three d NAND technology includes etching to cope with increasing number of stacking layers, firm deposition essential for device formation, cleaning without pattern claps and bonding technology again here. Finally, I will briefly touch upon the CMOS image sensor. Just like other devices, device hybridization is proceeding for image sensor. The sensor and logic are combined and AI processing is also added and you can see increasing applications. This shows challenges and solutions for CIS technology. The first one is hybridization. Hybridization is supported by bonding technology to support hybrid product of logic circuit and CIS. Silicon trench etching for device isolation and film deposition and etching for global shutter are also very important. I'd like to summarize my presentation. The semiconductor manufacturer processing is getting diversified and complex, which raises at value of SPE. This shows an update of WFE investment per monthly wafer size of 100,000 that I presented two years ago. Though there are some cases investment drops from two years ago, this is a result of improvement of the tool performance and productivity. This leads to the development technology in the industry, including customers. This is my summary slide. The market needs are getting more and more complex. And in order to address those needs, including the multifunctionality, the device evolution is accelerated. In the multifunction or functionality, of course, some of them can be addressed by existing process, but further technology innovation is essential. So as Ms. Sera said earlier, environment, SEGs need to be very important when we develop new technologies. This is what I want to emphasize. And when we develop the leading edge devices, actually, that has a lot to do with SDGs. That's one of the messages I want to convey today. Our company is implementing the process development on a worldwide basis, and we are working on the global collaboration inside and outside the company. So the following three presentations given by business unit will give you more detailed examples. Thank you very much for your kind attention. Now it's time for us to start the second half of the presentations. Mr. Akiyama, General Manager of CT SBU, will present Challenges and Solution for Advanced EUV Resist Process Technology. Ayama Kiyama, General Manager of CTSPS Business Unit. The title of my presentation today is Challenges and Advanced EUV resist process technology. I'll talk about process technology using leading edge coder and developer. This slide shows the features of CreamTrackRythios Pro Z EUV, our quarter developer for EUV lithography. In these days, as you know, there have been growing demand from IC manufacturers for finer resist patterning technology. EUV lithography is a solution for this demand, and this is Prozi EUV is essential to implement the EUV lithography. The primary strength of this is Prozi EUV are high reliability, high productivity and high versatility. As an in line process tool, this is Prozi EUV maintains 100% share. We have shipped more than 100 systems so far. High reliability and productivity are realized by two factors. The first is Resolute Pro Z platform featuring high speed transportation and processing capability. Over the past nine years, more than 1,600 Refill's Pro Z platform have been shipped for exposure system using various light sources. The second factor is that we have developed and installed EUV specific functions to the system to this system. I will explain the details of high velocity ET to address next generation EUV lithography in the next two slides. This slide shows the logic technology road map and corresponding advanced lithography technologies. As of 2021, the EUV lithography has already been used in high volume manufacturing lines. Scaling of minimum metal pattern pitch is going on in the five nanometer node, about 28 nanometer pitch is used, which requires EUV multi patterning. Final resist patterning is essential to realize further device scaling. Metal oxide resist, a new high resolution resist is expected to be introduced from the three nanometer node. An innovative high NA EUV lithography is to be introduced from the device node of 1.4 nanometer. Tokyo Electron is promoting R and D of our quota developer to enhance its versatility to address new EUV lithography technologies, including metal oxide resist and high NA EUV. This figure shows the proportion of layers using chemically amplified resist and metal oxide resist in each device node. For logic device, it is expected that the proportion of metal oxide resist featuring higher resolution will gradually increase along with the device scaling. For the time being, however, we think the proportion of chemically amplified resist remains high. The dry resist system of the competitor only addresses metal containing resists. By contrast, our quota developer is designed to address all EUV resist process, including chemical, the amplified resist, which accounts for the majority of the EUV lithography. High NA lithography is expected to grow in number. We are currently developing relevant technologies. There are still various challenges in establishing the next generation AUB lithography process. The first challenge is trade off of RLS, namely resolution, lineage, roughness and sensitivity. The second is patterning defects, which become increasingly challenging along with further device gating. The third is a challenge for high volume manufacturing, the necessary resist film thickness. When resist film thickness is reduced for better lithography performance, thin resist film will be damaged by etching to cause defects. When resist film thickness is increased, however, resist pattern will collapse and resist remains at the bottom hole after development process. In an attempt to overcome these technological challenges, we are working on total optimization of the patterning technology by combining the measures for the quarter developer technology and etching technology. Today, I would like to present some examples of those engineering efforts. Firstly, I will talk about the measures taken for chemically amplified resist, which has been used for a long time. In particular, today, I will present how we address resist patent collapse and increase process margin through the optimization of patterning processes, including etching. This shows the technology to prevent resist pattern collapse, one example of chemically amplified resist optimization. Along with pattern size scaling, resist pattern collapse become a critical problem in the wet development process. As shown in the upper images, 14 nanometer resist pattern with high aspect ratio collapse after conventional post development missing process. The lower images show the patterns treated with newly developed post development missing process. As you can see, even at 11.8 nanometer patterns, which are much finer than the target 14 nanometer resist pattern, do not collapse. By using the new post development rinsing process jointly developed material manufacturer, we have succeeded in preventing the patent collapse problem and increasing process latitude, process margin suitable for high volume manufacturing. Next, I will talk about formation of fine holes realized by optimizing lithography and etching process. As I said before, residual resist at the bottom hole after the development process is one of the challenges. If the residue can be removed, the etching process, the device yield will be enhanced. As a result of etching process optimization, 18 nanometer holes with 36 nanometer pitch are successfully transferred without any defects, defects, such as residue or kissing of two neighboring holes. The hole of 36 nanometer pitch will be used in the device node of 1.4 nanometer. Another example is shown in the figure on the right. In the lithography process, 23 nanometer holes are fabricated with feature 46 nanometer. This hole size was reduced to 13 nanometer through the optimized etching process. This technology to reduce hole size will be presented by ESBU later. We believe it is our prominent strength to realize this kind of optimization promptly because we have not only detection technology but also quota developer technology connected with the advanced exposure system. So far, I presented several samples of process optimization for chemical amplified resist, which has been used in high volume manufacturing mine for years. Next, I will talk about our initiatives for metal oxide resist or MOR. Today, I will present improvement of EUV exposure sensitivity, roughness reduction, countermeasures for defects and resist pattern collapse. This Slide shows the demonstrated performance of our newly developed post exposure bake oven. By applying optimum baking conditions, exposure sensitivity has been improved by about 25% without negative impacts on resist patterns. The exposure sensitivity enhancement will lead to higher throughput of EUV lithography system, drastic COO reduction is expected. The new oven will also improve the within wafer CD uniformity of resist patterns to 0.2 nanometer. For the metal contamination in the baking module, which is a specific concern of metal containing resist, the new oven meets the target for high volume manufacturing line. The new oven is suitable for the MOR, metal oxide oxide baking process. This shows the newly developed wet development technology. The conventional wet development process causes the resist pattern collapse problem when it is used for finer pillar patterns with 36 nanometer pitch for the future nodes of DRAM devices. The newly developed wet development technology is able to suppress the resist pattern collapse. This technology also improves exposure sensitivity by 25% without deteriorating uniformity of business pattern sites. This technology is expected to considerably reduce our customers' cost of ownership of EUV lithography by increasing EUV lithography system throughput through improved exposure sensitivity. We are also working on module solution for metal oxide resist incorporating etching technology. By optimizing our etching technology, we have improved uniformity of post etching pattern with us to 1.8 nanometer or less, which is essential to raise device reliability. For abridged defects, breaking interconnects, the defect density has been reduced below the initial target of 0.1 defects per square Through this improvement, even in the case of very fine interconnect of 15 nanometer, yield of almost 100% has been achieved. Our Kota developer technology has been highly optimized for metal oxide resist. We are on track in preparing for the introduction to high volume manufacturing line. Now I'd like to change the topic from technology to cost. Roughly speaking, there are two types of metal containing resist process being developed for high resolution. One is wet resist process of metal oxide resist that tell is now developing. The other is dry resist process in which resist film is developed by film deposition system and then dry developing development is performed by etching system. The latter is being developed by our competitor. In the dry resist process using CVD film deposition and dry development, it is essential to remove metal contamination from etch and backside of the wafers, which results in more process steps and higher manufacturing costs. By contrast, the wet resist process, which TEL is developing, does not need any additional process to remove metal contamination. It's also feature shorter turnaround time. Therefore, cost of ownership of wet resist process is expected to be about onethree of that of dry resist process. In addition to the benefit of cost of ownership and operating cost, the wet resist process is also found advantageous in terms of process performance. For example, it raises sensitivity to reduce EUV exposure time. It's easy for customer to adopt it. The final topic of my presentation is our activities for high NA EUV to further enhance resolution. In June 2021, TEL announced that we will deliver our in line quota developer for high NA EUV lithography system, which will be installed in the IMEC ASML joint high NA EUV research laboratory in 2023. Leveraging this research environment, we will collaborate with the partners to establish fine patterning technology for high NA EUV lithography ahead of others. We are working on optimization of pattern scaling solution to prepare for the high NAEUV lithography. This shows fine metal oxide resist pattern processed with the conventional EUV lithography system. The fine patterns of 12 nanometer half beach are fabricated by combining the wet resist process and our etching technology. It's demonstrated that wet development process realizes 12 nanometer half beach patterns with line etch roughness and line with roughness of two nanometer or less without causing any pattern collapse. This demonstrate that our new systems are promising for further pattern scaling in the future. We are planning to identify and overcome challenges together with our partners. This is a summary of my presentation. To address pattern scaling by using EUV chemically amplified resist, we have developed a new technology by leveraging synergy obtained through combination of the lithography technology and etching technology. We have developed a new technology for metal oxide resist to be used in high volume manufacturing with high performance and low cost. The same system can be used both for chemically amplified resist and metal oxide resist, which our customers will find convenient. To address high NA EUV lithography, we collaborate with the partners to provide advanced quota developer process solution to be used in high volume manufacturing of the future generation devices. This concludes the CT SBS business unit presentation on technologies for future EUV lithography. Thank you very much for your kind attention. Next, Mr. Wakui, General Manager of ES, will present the latest technological challenges and TALES activities in Etch. I am Wakui. I will present the Etching System business. First of all, I will talk about overall strategy for Etching Systems. We will continue making an effort to win PORs for hard process, high aspect ratio contact process, patterning process, interconnect and contact process and gas chemical etching process. For MLC and slit of NAND and capacitor of DRAM, we will maintain differentiation in processing performance and productivity. For channel four of NAND, we will introduce new equipment. For patterning, we will promote differentiation through combined etching and film deposition etching collaboration. For the interconnect and contact process, our expertise for logic, which is our strength, will be deployed to DRAM. For the gas chemical etching process, we'll expand its applications to new market segment. Let me start with memory business opportunity. We will address business opportunities for dry etching, which is increasingly adopted both in NAND and DRAM. For NAND, as shown in this slide, further multilayer stacking is going on by dividing layers into multiple processing. Aspect ratio is reaching seventy:one. In order to win PORs in the hard process, which increases along with the stacking, we will enhance matching performance, address high aspect ratio and help our customers improve productivity to mitigate their costs. This shows higher stacking of memory devices. As shown on the left hand side figure, three d stacking of NAND keeps going. The number of layers expected to increase further from the current one excess generation. And accordingly, NAND device will get higher and higher. For DRAM as well, when the current planar structure is replaced by the three d dimensional structure, higher spec ratio etching process is expected to increase, just like the case of three d NAND. Ongoing three d stacking will help the etching market keep growing. This slide shows the challenges of the etching process we face along with the trend of higher aspect ratio. From the left, you can see the etched profile of capacitor DRAM, channel hole, slit MLC of NAND. As aspect ratio increases along with multi layer stacking, there will be more demanding challenges such as formation of deep vertical profile, control of dimensional variation and selectivity against underlying layer. As shown in the right figure, a problem of depth loading, which suppresses etch rate at deeper area has a negative impact on etch performance and productivity. I will talk about our efforts to address these challenges. The figure on the right show how ions enter deep hole trench deep hole and trench. By making ion instant angle closer to plumb than before, we have enabled ions to reach deeper areas, which realizes accurate processing control and improve productivity. By leveraging this technology, we will win more PORs in the critical processes for which processing of high aspect ratio profile is essential. Next, I will talk about our efforts to enhance productivity. As I presented in the last IR Day, we introduced new platform, Episode UL into the market. It features flexibility to select the number of chambers to be mounted. It saves space by reducing footprint and it realized smart tool through an autonomous process control, including automatic part replacement and big data analysis. Episode ULs were delivered to multiple customers this year, helping the customers enhance their productivity. Next, I will present logic business opportunities. In addition to multilayer interconnect process, which is our strength, along with further device scaling, device structure will be varied as shown on the right. And also EUV lithography will be introduced. To address these trends, we will provide appropriate patterning solutions. Today, I will present how we address EUV lithography and gate all around nanosheat. This slide shows etching in the EUV lithography. Introduction of EUV lithography drives device scaling. But as shown on the right, the EUV lithography process induces defects and poor local critical dimension uniformity. Since AAV resist film is too thin for dry etching and features poor plasma resistance, there are problems such as poor hard mask performance and pattern collapse in patterning. To tackle with these challenges, we think it's important to complement the patterning process with etching technology. We will merge the film deposition technology and etching technology to overcome the challenges of the EUV lithography. The defects and poor local critical dimension uniformity caused by EUV lithography are addressed by repeating the film deposition deposition and etching process as shown on the top. Specifically, uniformity of whole size has improved in this case. Mask selectivity in etching processes improved by depositing protection film on the resist and selectively remove it as shown on the bottom. We also collaborate with IMEC and ASML, planning to provide patterning solutions for the future high NA ethnography. This shows how we address the transition of transistor structure from fin structure to Nanosheat. As one of the efforts to address nanoship fabrication process, we are studying the possibility to use chemical dry etching system to multiple applications. In these processes, it's necessary to etch silicon germanium, the black portion in the upper figure and leave uniform and smooth silicon film untouched. We plan to revel it to chemical dry etching, which can isotropically etch silicon germanium with high selectivity against silicon and suppress surface roughness so that we can win PORs. Finally, I will present initiatives to enhance our development and production capability in the Etching business. Last month, construction of Miyagi Technology Innovation Center was completed in Tokyo Electron Miyagi, as we announced. This center aims at creating innovative technologies and drastically enhance productivity. One of the options to achieve this aim is collaboration with our partners. This shows the roles of Miyagi Technology Innovation Center. The center is expected to play the following three roles to promote innovative manufacturing technology in our entire plants. Firstly, FIL or Future Tech incubation lab is founded to develop technologies to enhance performance of process to component, reduce lead time and mitigate environmental footprint as well as to develop new materials. The second role is innovation of manufacturing technology. We built PIL or Production Innovation Lab to study DX technologies to sense and analyze field data and explore possibility to use robot technology in assembly. To prepare for increasing demand and raise efficiency, we will develop new production systems and enhance automation of manufacturing lines. The third role is TC or training center to provide highest standard training by leveraging virtual reality and mixed reality, we will organize remote training as well. This is how we can enhance our strength. In this way, we can enhance the strength of the field, not only our company, but also our customers. Here's a summary. Driven by three d non patterning, high level of investment is expected to expected for etching system. Adapting to changes of device and addressing customer needs, we will continue with technology innovation for both memory and logic customers. We will enhance our development capability and production capability to be prepared for the further market growth in the future. Thank you very much for your kind attention. This concludes my presentation. Next, Mr. Ishida, General Manager of TFF will present TESS approaches for the next generation deposition technology. Ayamishida of TFF business unit. I'll present our approach to next generation film deposition technology needs in thin film formation business unit. In order to realize next generation devices with high performance, various changes of device structure are being studied. For logic device, Nanosheat is one of the promising options and all logic device manufacturers are expected to adopt it. On the right, you can see the structure of Nanosheat. For Nanosheat, multiple very thin dielectric films are essential. They must be resistant to chemicals and feature extremely low parasitic capacitance. Their thickness must be uniform in every direction. We must develop a dielectric film to meet all these requirement. TFF business unit is studying possibility to use a batch process. Why batch? We proposed batch process taking account of all the requirements. The clear advantage of batch process is its cost advantage and stable film thickness and quality. To control characteristics of the dielectric film, we are also evaluating possibility to use Varon. As we currently think thermal treatment can be used, we are planning to perform the process in batch furnace. Toward the future, we will find a way to expand its applications. In order to expand process options such as film deposition, etching and inhibitor of absorption and in parallel to maintain good film quality at low temperature region, we are evaluating multi processes by using single wafer processing. As low key film may become necessary in the future, we are evaluating new materials in batch furnace, which we didn't conduct it before. We are prepared to cope with future change of the needs and to address more demanding needs. We will compare the batch furnace and single wafer processing system in terms of technological needs and cost based on which we will provide most appropriate system to the customers. It is our strength that we can start this evaluation project together with the customer at earlier stage and discuss the direction of the new system. Next, I will talk about multilayer stacking, which is a technology inflection point in three d NAND. As stacked oxide and nitrate film need to be etched multiple times, it's difficult to obtain perfectly vertical profile in trenches and holes to their bottom. As a result, gap width gets varied. Atomic layer deposition features an ideal surface reaction. So NT333, our semi batch system using ALD technology has been widely used for three d NAND. In the case of multilayer stacking structure, however, because of its bottleneck profile and bowing, it's very difficult to deposit film without any boys in holes and trenches. To overcome this problem, we have developed a new technique to locally reduce film deposition rate. Specifically, film deposition rate is reduced only at the top of the profile to keep its top open. And then ALD film is deposited. This method can be used in single wafer processing system, but we decided to use semi batch system because the semi batch system can increase productivity, and it has been used in high volume manufacturing line. Next, I will talk about new initiative of silicon film deposition using batch furnace. Along with logic device scaling, at the stage just before shift to nanosheat structure, dimensions of fin structure are getting extremely small. Due to the minute dimensions, we encountered the problem of Fin structure erosion, and it becomes necessary to introduce a new process to tackle with this problem. Intel, we introduced architectural growth of sacrificial film. As fin is located at the substrate, the sacrificial film need to feature comparable quality to the substrate. To realize good quality film, we have integrated precleaning process into batch CVD silicon system, which is widely recognized in the market. As we successfully realized the new process by using cost effective batch furnace, the new process has been adopted in our customers' high volume manufacturing lines. The new initiative of silicon film deposition that I described in the previous slide might potentially have other For example, silicon silicon germanium stacking film used for Nanosheat, boron doped silicon film used as a stopper film in backside PDN and silicon silicon germanium stacking film used for three d DRAM. These potential applications, however, are extremely demanding in terms of technology because these films are required to feature outstanding quality. They need to be stacked and they need to be thick. Having said that, if these films can be deposited in batch furnace, such process will have very high cost advantage. As the batch process was pre cleaning combined is proven in high volume manufacturing line, we keep working on development to expand these applications. What I will present next is not film deposition, but film quality improvement by means of thermal treatment. High quality film must be deposited to enhance electric characteristics and reliability. It is also necessary to fix damages induced by film deposition process. To overcome these challenges, we are studying various treatment. Today, I will talk about D2, deuterium annealing. This process has been developed for three d NAND. Through collaboration with the customers, TEL has developed various processes to improve device performance and also developed hardware optimal for process conditions. Since this process performed in batch furnace, it features high productivity and can provide cost effective means to improve device performance. This is another example of firm quality improvement. In the previous case, as three d NAND features high thermal resistance, batch furnace is adopted. In the case of logic device, however, many processes, except for some front end of line process are subject to temperature restriction. There is an increasing need to deposit dielectric film at extremely low temperature, an innovative approach to use plasma treatment to modify deposit film is being actively evaluated. Our product, Super Eye, is one of the promising technologies as it can generate high density radicals at low temperatures. And this technology is now being evaluated. Potential applications of Super Eye includes modification of interlayer dielectric film in nanosheat and dielectric film for subtractive metal interconnect. Depending on technological requirements, we propose batch system, semi batch system or single wafer processing system and evaluate it. Here's another technique for film improvement. This uses single wafer processing system. By combining UV lamp and remote plasma, a very thin dielectric film can be deposited. Reaction of reactive spaces activated by UV lamp is very slow. And therefore, it features high controllability suitable for depositing thin high quality films. This technique has been adopted in high volume manufacturing line of some devices and by some customers. To address further scaling and oxidation of interface of thin film, this technique might be applied to logic nanosheet and three d NAND as well. This is a module solution to be realized by using Tel's corporate assets. It is not single effort of TFF. We intend to provide the solution to improve post etch local CD uniformity by using TFF's ICSIM, PVD system developed for MRAM. This hard mask film deposited in our PVD process features higher selectivity than currently adopted hard mask film. The film can be formed at temperatures, which CVD cannot handle and it features outstanding selectivity. We need to evaluate etching performance using this new hard mask. It's also necessary to evaluate removal of film at level in order to check whether the new hard mask material causes any problems for the integration. We are currently taking cross BU approach in these evaluations. We also have started sharing evaluation results with the customers. Here's a summary. In the next generation devices, demand for film deposition technology will be increasingly diversified. Though it is extremely difficult to develop new technologies, we are always required to reduce costs. TEL will pursue an optimum solution in terms of both performance and cost out of many options. We will provide technology solutions by combining the film deposition technology with pretreatment, itching and modification. We will expand cross BU and cross product collaboration as we introduce at the final portion of my presentation. We will provide an appropriate solution at the appropriate timing by sharing information with the customers in the evaluation process. Our customers agree and support this strategy of TFF business unit. New initiatives of technology development are in progress in many fields. We will develop leading edge technologies and corresponding process tools to raise the customers' trust and expectations and expand our own business. This concludes my presentation. Thank you very much for your kind attention. Now we'll have question and answer session till 05:30. We will receive questions both in Japanese and English. But as our attendees are on the Japanese channel, please allow us to restrict verbally asked question to only in Japanese. When you ask question in Japanese, please hit Raise Hand button on Webex. For details, you are currently requested to refer to the instructions attached to the e mail. I will call name of the person who ask a question one by one. Please check the chat box on Webex as our Secretariat will inform you in advance that you will be the next person to ask a question. Our Secretariat will unmute you when you ask question. If you ask a question in English, please use the chat box to send the question in text together with your name and affiliation to the Secretariat. We will refrain from answering a question if no name or affiliation is given. On the Japanese channel, I will read up the question translated into Japanese, and our attendees will give an answer in Japanese, while on the English channel, it will be simultaneously translated into English on a real time basis. For questions verbally asked in Japanese, please allow us to limit one question with one follow-up question. For English questions sent in text, I'm very sorry, but we will receive one question without a follow-up question. The first question, sorry. So Mr. Yoshida of Shi LSA Securities Japan. Mr. Yoshida, please. I am Yoshida of CLSA Securities Japan. Thank you very much for your very detailed presentation. The first question is about Slide 101, WFE investment. Per 100 ks wafer starts per month. For Logic, in the past, you presented the value for five nanometer, 20,000,000,000. However, this time, for two nanometer, 21,000,000,000. Because of the efforts of the two vendors, the focus has been revised downward for five nanometer to three nanometer and two nanometer. When you look at the investment, the increase is rather mild. So the solid graphy intensity increases, some manufacturers said that what cost have been will be reduced according to your prediction. In the past, about 15% to 20% increase is expected for investment from one generation to another. I want to understand the reason for Memory, NAND, triple stack and three d DRAM. When they start, what happens to the WFE investment and breakdown by process two? I want to hear about some future of the Memory. REPRESENTATIVE:] UNIDENTIFIED Doctor. Sekibuchi, please. It's a difficult question. So the cost increase is driven by exposure and patterning. I think patterning and exposure lithography accounts for the huge amount of the very big amount of costs. But three nanometer and beyond, in order to reduce cost, there are various method, combination of various tools to produce the devices that will become more important in the future. For patterning technology, as you heard from the business unit, we are now focused on the combination of different devices at the same time, the production technology. So the productivity is enhanced where you can reduce cost as well. So there is one addition from IR. So this is the prediction based on our process flow. So this is capital intensity based on our estimation. So customers' three nanometer or two nanometer node are way in future. So they are not fixed one. This is just the estimation prepared by TEL, our company. So for memory, in that sense, you haven't produced your own estimated flow yet. Is that correct? Three d DRAM, for example. For three d DRAM Doctor. Sekiwaguch, please. For three d DRAM, actually, it's way ahead, so things are not yet fixed. That's what I said in my presentation. On Page 92, key modules, you can see the stack formation, cell transistor formation, capacitor formation, all those area, there is room for technology innovation. So as of today, we can just give this number based on current assumptions. One So Etching Technology, Slide 130 Page 130, gate all around nanosheets selective etching. Gas chemical etching advantage is shown over here. But for the wet etching, I think there is another option using the wet etchings. What is the difference in Cosmetometer two? And which technology will be more promising at this stage? Park Lee san, please. Again, difficult question again. So technologically speaking, so etching selectivity and high uniformity, we need to pursue those two requirements. So that's gas chemical etching. I think that gas chemical etching has some advantage because of those two reasons. But your question is about whether wet etching or gas chemical etching, that is very difficult to answer. But we believe there are some processes which only gas chemical etch can handle. Next question is from Mr. Wadaki from Nomura Securities. I learned a lot from today's session. I have a question for Etching System to Doctor. Sekeguchi and Mr. Awakui. So now we are talking about Etcher Step number of steps because what happens for high end A with SPIE, I saw some information for three nanometer, two nanometer M2 for EUV with LALE. EUV, Sulphur in Dock two are to be used. If that's the case, maybe we should use etching system 10x, then you can sell a lot of etchers. Then after that, all those things will be replaced by high NA. That's the road map. Then all of a sudden, etch order will be decreased. But in the case of three nanometer or three nanometer high NA for logic etching, how do you view the number of etching processes in logic in three nanometer or two nanometer by using high nano NA? For two nanometer, three nanometer, things are still uncertain in the customer side. But so I think they are gradually come up with some integration flow. So in your question, you pointed out the patterning. It's getting more complicated in the beginning, so number of etching will increase. That is the starting point. However, ultimately, customer will adapt in order to reduce device cost. So we need to provide the most simplified process. Integration flow should be designed by using customers' wisdom. And ultimately, maybe number of the processes a bit difficult for us to give you the number of processes, but we don't see the explosive growth of the etching process when we see the next generation up to until N3 or N2. So self aligned block, I think that require 10 etching process. I think this estimation should be not so round. For patterning, maybe Doctor. Sekiwuch, please. Mr. Waraki, could you repeat your question once again, please? For self aligned. I said self aligned Block two. One block requires four etching processes. And when you carry out two blocks that require four etch processes, in addition, you need to carry out LE LE in advance. So 10 etching process might be required. I think your estimation is not so wrong. So for three d reRAM, when three d RAM will come? And different from etcher, bit line, etching, the word line needs to be etched and capacitor needs to be etched. So number of etching process will be increased. And I think that will be good news for the etching business. What do you view, Mr. Sekeguchi and Mr. Wakuhi, for timing? Page 91, Slide 91. HBM for three d DRAM, 20%, 26% or 27%. That's the HBM estimation. So that's when the three d DRAM might appear. So number of etchings processes, it goes vertically in the past, but it go now laterally. So each required film deposition and etching for each layer. So number of process, of course, it depends on the number of capacitor, but I'm sure that the number of process increases. That's true. You very for your answers. You very much for your question, Mr. Wadaki. Next question is from Mr. Yamamoto from Mizuho Securities. Mr. Yamamoto, please. Mr. Yamamoto, could you unmute you, please? Can you hear me? Yes. I'm sorry. I am Yamamoto of Mizuho Securities. For ESG and two development, my question is rather vague, I'm sorry for that. So CO2 emission scope when you think about Scope three for CO2 emission, so direction of the tool development will change or not in order to improve the CO2 emission in Scope three. Do you have any idea to include something new in the development process or the direction conventional direction remain unchanged? And as a result, the CO2 emissions will be reducing. So some competitors said green, but they try to enhance or appeal their process performance or tool performance. Do you think direction of development will change to reduce CO2 emission in Scope three? Sega san, please. I am Sega. Let me answer to your question. At present, the productivity enhancement, that direction, conventional direction is to be pursued. And at the same time, we can enhance green. And I think we can pursue those two target at the same time. And as I said earlier in my presentation, the regulations are getting more and more stringent. And customer environment, there are different customer requirement depending on their environment. So we need to focus on those situation to decide what to do, where we need to focus in our development. So in the past, do you have the conventional reaction of the development? And there is no big change in your direction of development. For mainstream development, yes, that's correct. So users, so for Green, when they select the tool, do they have any are there any users who focus on Green? Or even if for the critical ones, they cannot prioritize green, but for other area, some users just focus on green when they select the tools. Do you have any information getting from the customers? UNIDENTIFIED I am Kawaii. Good Right. So there are three stages. So two, performance in the ESG, CO2 emission reduction for semiconductor device performance to performance and the site activities. We are focusing on those three areas for CO2 emission. So customers when from the viewpoint of the customers, for example, low power consumption for device and to emerge device two devices into one, that sort of thing is required. But the green performance, it should be part of the true performance. That's how we understand. And how I'd like you to understand situation. In other words, so the per unit area, so when a clean room is operating, the device output per unit area of clean room that has to do with the productivity of the manufacturing line. That should be one of the keys in the tool selection done by customers. So within this limited space, how much devices they can produce, that's very big factor in the customer's selection process. At the same time, in our company, concurrent development is now going on. So development and production. So we are always thinking about the mass production when we design the process tools because in the future, so three nanometer, two nanometer, three d NAND, 200 or 300 layers comes, then two to tool matching and chamber to chamber matching. So that requirement will be getting more and more severe. So the matching should be considered when we design a new tool. So tool uptime should be increased, yield is enhanced. These things also has a lot to do with the green or CO2 emission reduction. And for the customer to establish the fab with lower CO2 emissions, that will become more and more important. So each customer has their own formula for green. So they have I think green specifications should be one of the criteria for selection of tool, and that is required. And also legal requirement for environment, We need to pay attention to the legal requirements for environment. Chemical recycling need to be considered as well. So when we make a proposal to the customer, at the same time, we need to enhance the alliance with our partners. So this is how I can answer to your question. And eCompass, we have established the new initiative, and that is one of the background why we established eCompass. Thank you very much. That was very clear answer. Thank you very much for your answers. Mr. Yamamoto, thank you very much for your question. One request from us, at present, the simultaneous translation is carried out. So could you speak a bit slower for the interpretation? REPRESENTATIVE:] So next question is Mr. Shimamoto of Okusan Securities. Am Shimamoto of Okusan Securities. Can you hear me? Yes, we can hear you. Thank you very much. So from me, so about the growth story, I heard your growth story now. So 30, up until 02/1930. For each device, you have the device road map. And for each process tool up until 02/1930, what is your expectations for the growth? And could you show me some order of the growth? So Kota Developer, dry etch, film deposition cleaning, prover, so you have various products. So for those different, could you just give me some clue about the growth story toward 02/1930? REPRESENTATIVE:] Mr. Shimamoto, so it's the general road map. So your question is about general road map. What would you like to know about specifics about the process to specific road map? Rather than specific, I want to understand general road map till 02/1930. Logic and Memory, you have presented the road map for Logic and Memory. So what is your expectations for growth? I want to know which tool has the high expectation for the growth. That's the gist of my question. Sekirisan, please. So I think the President, Mr. Kawaii, will give you the answer on behalf of the company. But the number of processes from the viewpoint of the number of process increase, the logic road map on Page 75, could you refer to Page 75? So the FIM structure, front end of line will be replaced by Nanosheat. In this area, film deposition and etching to so the CD, the critical dimensions have been determined by dry etch plus dry etch surface. So they were important. So nanosheat structure is a spokessheet, so etching proportion growing. At the same time, film deposition proportion also increased. Also Cleaning, direct process increased as well in number. So I think all of them will be growing not evenly, but each process increases. And the fine patterning will become required. So that's the story for Logic. As for DRAM, so the scaling, device scaling will get slowed down. That's what I said. On Page 91, you can see the road map on Page 91. And the device scaling, the patterning, ARF emerging lithography and EUV lithography will be used one more. So basic structure remain unchanged. And 2026, three d DRAM comes out. So that's when the changes occur. And after that, as I said, so film deposition and etching are expected to grow. For NAND road map on Page 95, over here, what is increasing is number of tiers and number of stacking, number of layers for stacking. So when more and more layers are stacked, the capacity will increase. That's what the current structure is. That remain unchanged. Thank you. Understand. So for each device, depending on the use, so the important process tools are different. Thank you very much REPRESENTATIVE:] for your answer. May I I am Kawaii. I would like to give some additional answer. As we said before, 2020, the semiconductor device market is about $400,000,000,000 By 02/2030, dollars 1,000,000,000,000 or more is expected for 02/1930. Semiconductor market grows above $1,000,000,000,000 So our customers' market, when you look at next decade, the market will be doubled. That's the current situation. So when I look at WFE, so WFE market also has the strong potential for growing. So in the future, now there are four products: Kota Developer, etcher, cleaning and film deposition. So in those four products, they are our core products. And we are focusing on those four area: higher capacity, higher reliability, higher speed and lower power consumption. So these a lot to do is the patterning performance, and those four are expected to grow drastically. And this area for our company, they are the core business at this moment. And in our company, so we have the broad portfolio, plasma technology and pressure control, thermal control, chemical technology and also bonding technology as well. So we have various technologies as well. So we are going to provide the technology that customer will need in the future by leveraging our strength. And the semiconductor market is expected to be be doubled in size toward that kind of high potential market. We are going to promote the technology innovation so that we can contribute to the semiconductor market, at the same time, I'd like to expand our business. That's my additional answer. That's all from me. Mr. Shimamoto, thank you very much for your question. Next question is from Mr. Hiragawa from DO B of A Securities. Mr. Hiragawa, please. I am Hiragawa of B of A Securities. I have a question for Etching. Page 125, 125. This time, incident get closer to 90 degrees. That's what you said in your presentation. So what sort of tell proprietary technologies are employed? If possible, I want you to explain your technology and your competitive technology. And as a result, at present current aspect ratio compared with your competitor, what is your status for the high aspect ratio? So this includes my follow-up question actually. So Wakyu san, please. So for the incident angle of ions are getting closer to 90 degree. That's what we are working on. As I said, in my present as for the direction, that's RF powerful bias of ions, which should reduce frequency and increase power and also the pulse technology. So out of those options, we try to come up with optimum solution. That is the uniqueness of our company. Our competitors, the comparison with our competitor, so the information that we have, it's a bit difficult for me to answer to that question. So as far as our company is concerned, three technologies are to be combined in the optimal way. This is how we try to differentiate ourselves from our competitors. So for technology, it might be difficult to compare your technology with your competitors. But current aspect ratio, could you just give us some comments on the aspect ratio, please? In my presentation, I said seventy:one. That's what I said, at present. Current aspect ratio of specification is seventy:one, and we are developing technology to satisfy that specification, and we try to differentiate ourselves from the competitors' technologies to satisfy the aspect ratio of seventy:one. I think in a future generation, aspect ratio gets much higher and higher. So we are working on the current specification for seventy:one. And I cannot give you any more answers about the future technologies or future aspect ratio. Thank you very much. Mr. Hiragao, thank you very much for your question. Next question is from Mr. Yasui of UBS Securities. Mr. Yasui, please. I am Yasui from UBS Securities. My question is about the technology road map toward year 02/1930. For Logic, DRAM and NAND, you presented the road maps toward 02/1930. As for Plan B, for example, there are some game changer device for 02/1930. Are there any possibility of changes game changer from two d to three d NAND flash memory is putting forward, the device manufacturer competition changed and etching demand increased. So five years to come or ten years come, if this comes, the demand might change. Do you have such kind of potential game changer? That's my first question. UNIDENTIFIED Okay. Actually, one after another, I encountered a very difficult question. It is true that floating gate from floating gate to three d NAND, when the change occur from floating NAND to three d, the change was rather drastic. And customers didn't expect such high speed of change rate of change. For three d DRAM as for three d DRAM as well, as for the possibility, yes, there is a possibility. We cannot say anything decisive and technology development. We need to refer to the future technology development. That's first thing. And second one is system integration. So that's what I said in the beginning of my presentation, system integration. So what we are very active is back end of line, so various memories are to be embedded. That's the development. We are working hard. For example, memory and logic co embedded together. So that type of device hybridization. So we have that sort of activities. So device competitive edge increases in that way. So now paradigm shift takes place and maybe in the future, hybrid device might increase. REPRESENTATIVE:] That is another possibility for the future. And my follow-up question is for memory. So you talked about next generation Memory. There are many of next generation Memory. So I think that possibility is a bit behind. Do you think you don't think application does not grow so much? At present, the existing devices will continue to be evolved. That's how we view the future DRAM continue NAND also continue. However, for early RAM, PC RAM, MRAM, actually, they are the big issue for embedded area, and we are working on development steadily. So it's a bit bad news a little bit, but non volatile memory. And also neuromorphic is also included. Thank you very much, Mr. Yasuke for your question. Next question is from Mr. Nakanomio of Jefferies Japan Limited. I am Nakanomio from Jefferies Japan. So Page 115, 115, the comparison with dry resist. On the bottom, I can see that the cost and operation benefits, at the same time, performance. The compared with dry process, wet process is more advantageous. That's what you say in your slide. So when the device scaling moving on, are there any theoretical limits? Are there any potential for dry resist? Akema san, please. For dry resist, the performance potential or advantages, not only for performance. I think as on Page 115, what is more advantageous? But generally speaking, so dry processing when you use dry processing, the patterns are resistant to the pattern collapse. That's what we said in the past. However, we are working on wet process development. And we are now working on challenges. And that's what I said in my presentation. The pattern collapse can be prevented even for the future scaling. We have we try to develop such kind of technology. As I said in my presentation, there are some data as well as the data considered. As for the pattern collapse, the wet process performs as good as dry process to prevent pattern collapse. So against dry process, what we are concerned a lot is the pattern collapse when we developed wet process. So up to until when? Are there any limit, theoretical limit or something? So you mean the wet process can prevent the collapse pattern collapse? So in the case of wet process, the surface tension takes place. So surface tension, the lateral force will cause the pattern collapse. However, if the surface tension is prevented by adding the development process. In the development process, we have additional chemicals, coating or rinsing process. We have some technology incorporated to cancel offset the surface tension. So we are doing some collaboration with chemical manufacturer. I'm sorry, I cannot say any limit, but this is what we are working on to take actions against the pattern collapse by developing new technology. My follow-up question is about on slide maybe similar question to Yamamoto san. The Slide 38, we talked about downstream CO2 emissions. I can see some figures. When I look at figures of CO2 emissions in downstream, so I think your products generate CO2 a lot in the use stage, but those figures do not have so much big meaning. For example, depending on the amount of products to be shipped or the number of devices to be produced. Even more devices are manufactured, the CO2 emission increases naturally. So what users are concerned is the CO2 emission per device or power consumption per device. My question is, so those figures reduced so as for KPI, reducing those figures of CO2 emission does not have so much meaning. Well, how do you view this CO2 emission in downstream compared with the competitors? Segou san, please. So quantitative comparison with competitors, I cannot give you any answer to that. When we sell more products, as you said in your question, the amount of CO2 emission increases naturally. And the customer felt the CO2 emission increases when they produce more devices. But as I said earlier, the power consumption, water consumption and CF gas and chemical, if by reducing those consumption, so when we convert it to the CO2 emission, we can reduce converted CO2 emission or CO2 equivalent. So as a whole industry, we can make some contribution to the reduction of the CO2 emission. At the same time, we can contribute to the mitigation REPRESENTATIVE:] of the global warming. You very much for your answer. May I say I am Sekiiguchi. May I add some comments? On Page 67, you can see the environmental KPI and on the left hand side, when you look at left hand side, there is a figure. You can see normalized KPI metric on the vertical axis and you can see technology node on horizontal axis. What is plotted over here is so performance changes from one node to another. The number of transistor element per transistor element, the performance takes place or area per transistor and energy to be consumed for production, how they are reduced and process cost and pure water or the pure water consumption. So when you look at this figure, per transistor, one unit transistor, environmental footprint impacts are expected to reduce. Of course, the number of transistor when the number of transistor to be produced increase, overall, impact increase. But when you use the leading edge node, you can reduce the CO2 or environmental impacts as a whole. That's the message that I wanted to convey by using this slide on Page 67. So this plot might be changed depending on each individual device. This is total cost. So this includes all the process costs. So of course, product, we have the figures of cost for each product and cost impact might be different depending on the type of the process. Thank you very much for your answer. Ayankawaii, for ESG, CO2 emission reduction. For that for competitiveness edge of our company from the viewpoint of the competitiveness, so year 02/1930, CO2 emission reduction. So 30% reduction is our target toward the year 2030 when our process tool is in operation. And also in this area, in this industry, these figures or targets are the highest compared with other competitors. Among the goals announced by other competitors, this is the highest level of the goals. Of the importance. So semiconductor WFE semiconductor wafer fabrication equipment, that has a lot to do with the competitive edge. So for each production, the productivity is enhanced. At the same time, Pat, when for patterning, other than our company, the number of processes than our process, for example, EUV lithography process. So when we propose some idea to contribute to EUV lithography. We want to come up with some solution in terms of environment, cost and production. So I would like to work on those areas as well. I'm sorry, this is my additional comments to you. So I'm afraid I didn't I answered to your question properly. Thank you very much. I'm sorry, my question was not so well organized. No, no. Thank you very much for your good question. UNIDENTIFIED Thank you very much, Mr. Nakano mio, for your question. Next question is from Mr. Ishino of Tokai Tokyo Research Center. I am Nishino from Tokai Tokyo Research Center. My question is slightly different from technology. But generally speaking, five nanometer foundry logic price is about $15,000 three nanometer, 25,000. So the chip manufacturers, the chip cost is about $50 to $80 about 60% increase in chip cost from the viewpoint of the IC manufacturers. So ultimately, the semiconductor supply tight and end user, the consumers, pay more through the cost transfer, but 60% increase will have the impact on the final retail price. So now in this our today's presentation, three nanometer and you talked about EUV lithography as well. At the same time, as you on Page 115, cost of wet process using metal oxide resist is onethree of cost of dry resist process. Then the three nanometer foundry cost increases, then high NA lithography means are getting putting forward or metal oxide resist. From the initial estimation, the needs for metal oxide release are appearing faster or sooner and many other companies are emphasizing their effort on metal oxide resist. So there is some breakthrough in cost. So which product is more affected? And onethree by are there any drastic reduction cost by introducing cost? And could you just explain that sort of cost trend, please? You very much for your question. Akamasan, please. So on Page one hundred and fifteen, one hundred fifteen, this figure as for this figure, I would like to give you more detailed explanation on this figure on Page 115. So you said 3x. The major difference is, as you know, so the quota developer at present is connected in line with EUV lithography system. Therefore, after resistors coated, the exposure and baking and development for that process, they are connected in line. So all those four process steps are completed within the in line system. Compared with that, when we use the dry process, the CVD tool used for the resist film deposition And after that cleaning process is necessary to clean the wafer. And after that, wafer goes into the exposure system. And after that, wafers are transported to another system for baking. And after that, the dry etch is conducted. And after that, cleaning need to be conducted. So as I said now, there are five or six more additional processes are necessary in the case of dry process. So those additional processes are major factors of the 3x difference of the cost between wet and dry. And another thing you just asked me, high NA lithography, as I said in my presentation, IMEC ASML together with those two organization, we are now evaluating technology in joint laboratory that will start from 2023. So when this technology will be used in the mass production, maybe from N1.4 or beyond year 2025 or 'twenty six. So that is the fastest timing, and I don't think that will change. And metal oxide resist application, the metal, 30 nanometer pitch and beyond, the metal oxide resist will be actively adopted by our customers. That is the general trend among our customers. Thank you very much for your answer. My follow-up question is so ASML IR Day, the other day, so High NA 2025, these are five units to be shipped. But according to your presentation, yes, 2026 and beyond, High NA lithography is not to be used for the mass production or a large amount of metal oxide resist will be used beyond 2026. Is that correct understanding? And existing EUV lithography system is about 20,000,000,000 yen high NA lithography is 30,000,000,000 yen for one unit. So in such a case, your process also process tool price increased by 50 percent just like the lithography system. So that will not contribute to the cost conservation or cost saving. Could you share your idea with us please on those two regard points? Your first point as for your first question, IMEC from IMEC, IMEC announced some information. As I said, 2023, EUV in rough high NA lithography system starts its operation. And they are going to develop technologies to install that to the high volume production area for three years. And against that, ASML, the TEL and the chemical vendors are supporting that technology. So year 2026 is the target year. And so conventional EUV lithography innovation speed, I think that three year plan is rather aggressive plan. When it comes to price from our company, we are not able to give you any comments on price. But one thing for the quota developer, as far as quota developer As I said earlier, so wet process for this wet process, so the chemically amplified resist, metal oxide resist, those two can be processed in one system, one equipment, which is rather unique. Therefore, so our system can handle both then the number of module increases. So compared with the process only processing chemical amplified process compared with that configuration, the process tool price is expected to increase slightly. But it depends on the configuration or specification of the process tool, which affect the process. I cannot say how many percentage of the increase is expected. I cannot give you any specific numbers. One more Full up answer. High NA EUV are not to be used for all layers. So even if we say high NA EUV is introduced, maybe the several layers for this first node. So it does not mean they need to invest several 100,000,000,000 yen for additional investment. So including front end and back end, it depends on devices. There are tens of layers, and all of them will use not all of them will use the high NA EUV lithography. So the cost increase, how do you think about cost increase? Could you repeat your question once again, please? From five nanometer to three nanometer, foundry cost is expected to grow increase. And how do I need to understand that? From the process to vendor, you don't see that as a big problem. Is that correct understanding? The foundry cost. Yes, please. So three nanometer foundry cost price. So the set manufacturer and design fund company to be that manufacturing are contracted out to the foundry. So when foundry receive the manufacturing from fabless, maybe that should be $15,000 for five nanometer. So when it comes to this three nanometer, the price goes up by 60%. Does that affect your business as the tool vendor? For the node, for example, three nanometer, the cost is so and so. So for our customers' design and integration methodology, depending on the choice of the design and integration techniques, different. So we are not able to give you any comments on that regard as a tool vendor. But as I said earlier, the but when we increase the productivity of Process two or enhance the yield, This is how we can support our customer to reduce their production and manufacturing cost. I am So for semiconductor, so now we are shifting from the product to the value. So semiconductor used to be device of the industry, the essential building block of the industry and high end area. So high value added added value is increasing higher and higher. In order to realize some solution of value, this technology is essential in that area, critical area. As for the process tool vendor, of course, we are working hard to enhance productivity and yield enhancement. So we try to pursue the technology innovation, which is essential for us as a tool vendor. But we provide so that provide the values and customer can recognize that sort of values sufficiently. The customers and we are supposed to reduce costs, that's not the story. And digitalization and green digital and green, and we try to contribute the dream inspiring society. So I think we can provide sufficiently high added value in our business environment and there is a huge growth potential. And the technology innovation in semiconductor continuously will accelerate it according to my understanding. And as Sekiro san said in the beginning, the hyper mass area for that particular area, there are legacy nodes are to be handled. In that area, hyper mass area, the cost reduction or price reduction is the cost options. And our Fit Solution business contribute a lot there. So this is how this is not the concern, but we think there is a huge potential for growth. About your question. Thank you very much for very thorough answer. Thank you very much for your question. There are quite a few questions, but now it's time for us to close the session and disclose the Tokyo Electron IRJ. For those questions we are not able to answer today, we will upload answers to Q and A page of our website. And please send the text of the questions if you want to raise questions in text. Thank you very much for joining us this batch of busy schedule today.

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