Good afternoon. My name is Dilem. I'll be your conference facilitator today. At this time, I would like to welcome everyone to our presentation and Q&A session with Scott DeBoer, Micron's EVP of Technology and Products. All lines have been placed on mute to prevent any background noise. After the speaker's remarks, there'll be a question and answer period. If you would like to ask a question during this time, please press star, then the number one on your telephone keypad. If you would like to withdraw your question, press the pound key. In order to allow as many analysts to ask a question as possible, please limit yourselves to one question. Thank you. It is now my pleasure to turn the floor over to your host, Farhan Ahmad, Vice President of Investor Relations. You may begin.
Hello, I am Farhan Ahmad, Vice President of Investor Relations at Micron. Thanks for joining us for today's presentation and Q&A session. On the call with me today is Scott DeBoer, EVP of Technology and Products at Micron, and Dave Zinsner, our CFO. We request that you keep questions focused on topics related to today's presentation. As a reminder, the matters we will be discussing today include forward-looking statements. These forward-looking statements are subject to risks and uncertainties that may cause actual results to differ materially from the statements made today. We refer you to the documents we filed with the SEC, specifically our most recent Form 10-K, for our discussion of risks that may affect our future results. Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance, or achievements.
We are under no duty to update any of the forward-looking statements after today's date to confirm these statements to actual results. I'll now hand it off to Scott.
Thanks, Farhan. Good afternoon. I'm Scott DeBoer, Executive Vice President of Technology and Products at Micron Technology. Over the last few years, Micron has focused on closing the gap with competition in both DRAM and NAND technology through faster node transitions. In parallel, we've put significant focus on increasing the mix of high-value differentiated solutions. We have aggressively focused on execution and driven quality leadership. As we look ahead to the next phase of our journey, we envision the new Micron as an industry technology and product leader. Now that we've caught up on technology, our target is to introduce leading technology nodes at a typical industry cadence while maintaining our improved competitive position. In the last few years, we've targeted our supply growth to be roughly aligned with industry demand growth. We believe this strategy helps reduce overall industry cyclicality and supports healthier market conditions.
We're committed to maintaining this strategy. On the product portfolio side, over the last few years, Micron has transformed our product portfolio by increasing our mix of high-value solutions. 80% of our NAND bits are now comprised of high-value solutions. Looking ahead, there are many more opportunities for differentiated products as the world moves towards heterogeneous computing. Today, I'll provide an overview of Micron's technology and product strategy, as well as update you on the future direction of our key technologies with a focus on NAND and DRAM. Starting up with our strategy. The new Micron is strong and getting stronger, with greater R&D efficiency, a broad technology portfolio, and the industry's best talent. About a year ago, we integrated our technology and product organizations under my leadership to drive greater R&D efficiency and customer value.
This tighter vertical integration has made us more agile, uncovering opportunities to incorporate customer product requirements directly into our R&D technology and design roadmaps at the die level. The result is faster time to market, differentiated performance, best-in-class quality, and cost competitiveness for our customers. This integration of technology and products and the result is a great example of how the new Micron is continually adapting to drive innovation and improve execution. Micron has the industry's broadest portfolio of technologies, delivering economies of scope via R&D efficiencies and revenue synergies, such as the ability to bring our customers differentiated solutions across the entire memory and storage hierarchy. We are the only company in the world with DRAM, NAND, and 3D XPoint products, and the only manufacturer of 3D XPoint.
We are pushing the boundary on performance with the fastest DDR6, and I'm proud to announce that we have begun revenue shipments of our first HBM2E products. We are also expanding our reach into the high-capacity cold storage market with our industry-leading QLC products. In the space between DRAM and NAND, our 3D XPoint technology provides a cost and performance value proposition that will grow as new computing paradigms evolve. Micron is uniquely positioned to attract the industry's best talent globally with R&D teams in the U.S., Italy, Germany, India, and China, and technology development co-located with manufacturing in Taiwan, Japan, and Singapore. We're confident that our global talent is a significant competitive advantage fueling our innovation. Over 50% of the new hires in R&D have Master's or PhD degrees. The strength of our team is also evident in our growing patent portfolio of over 44,000 granted patents.
Micron has been recognized as a top 25 company in terms of U.S. patents and has been recognized as a best employer for diversity and a great place to work. In the last year, approximately 25% of our R&D new hires have been women. In just over a year, the number of women inventors and patent holders at Micron grew by 80% year-over-year. We're extremely proud of these women supported by WIM. WIM is our program for Women Innovators at Micron. We are committed to furthering diversity, equality, and inclusion at all levels across the company. Turning to our core technology, and starting out with DRAM. We're really excited about our progress on the 1-alpha DRAM node. This node will offer tremendous improvement on bit density, performance, and cost, and significantly improve our competitive position in the industry.
We expect this node will be in volume production in the first half of calendar 2021. As 1-alpha ramps, it will provide Micron with a very good cost structure while also delivering substantial performance improvements. It will enable the industry's lowest power mobile DRAM with a 15% improvement over our prior generation and will include a roadmap for the highest speed DRAM available across a comprehensive portfolio. Our 1-alpha node has a very impressive 40% increase in density versus 1z- nanometer. This includes a 10% increase in density, specifically from design efficiency alone. Following this node, we do expect to return to a more normal bit density growth. We are truly excited by the progress we've made on our 1-alpha node, and we have an exciting roadmap ahead that builds on this momentum.
Micron's DRAM roadmap will enable continued scaling with cost and performance improvements at industry pace over the next decade. This roadmap contemplates the deployment of High-K CMOS at the appropriate time to cost effectively improve performance while lowering power consumption. We are making solid progress on our 1-beta node currently in development as well. We have extensive pathfinding work focused on the nodes beyond that. We continue to evaluate EUV and are prepared to implement EUV when the time is right for Micron. Our 1-delta node may use EUV or multi-patterning, depending on a variety of factors in our pathfinding analysis. As we have previously stated, our multi-patterning immersion lithography provides a cost advantage relative to today's EUV, and our assessment will continue to do so for the next several years.
Micron's proprietary multi-patterning technology combines our expertise in process technology and lithography with the most advanced immersion systems to provide a cost-effective roadmap. In addition, the quality and performance that we are able to obtain in our DRAM products is highly dependent on the extreme care we take in minimizing all varieties of pattern variation that may occur during wafer processing. Our current lithography technology is a key enabler of our exceptional level of end product quality that our customers depend on. This sets a high bar for us to ensure that we incorporate EUV at a time when it is capable of delivering to our high quality standards. As we continue to evaluate EUV, there's no question that the EUV ecosystem and EUV tools will continue to improve, but for the next couple of nodes, they will not meet our industry-leading quality standards.
We expect EUV will ultimately be capable of providing benefits for DRAM. We are confident that our implementation of EUV for future DRAM is well aligned with that capability timing. Next, I'll move on to NAND. As a result of our strong execution over the last two years, we have successfully transitioned to replacement- gate technology, enabling the world's highest layer count NAND at 176 layers. There were three fundamental ingredients we combined to make this happen. Our replacement- gate architecture, CMOS under array, and advanced charge trap process technology. Our 176-layer NAND has 40% higher layer count and a 30% smaller die size as compared to our leading competitor's latest offering. It features an industry-leading maximum data transfer rate at 1,600 MT/s , which leads to faster system boot up and improved user experience across multiple end markets.
We also see better power performance capability with greater than 2x improved power efficiency and write performance versus Micron's 96-layer 3D NAND. This capability is essential for addressing future high-end mobile applications. Our first-generation 128-layer replacement- gate node was designed to be a limited volume node to demonstrate the technology and obtain early manufacturing experience. As expected, node-to-node qualification time was substantially greater than for prior transitions. Through outstanding execution across the Micron team on our 176-layer node, we dramatically improved the qualification time and reestablished a competitive position. Now that we've put ourselves in a strong competitive position, we expect to pursue future node transitions at a typical industry cadence to maintain that position. Our roadmap continues to provide 3D NAND scaling and cost reductions for several generations. Beyond 176-layer, our 2XX replacement- gate NAND will continue to deliver best-in-class technology and industry-leading performance specifications.
Beyond 2XX replacement- gate, we're in early development for the next node and pathfinding for subsequent generations. Additionally, we're focused on extending QLC leadership to accelerate hard disk drive replacement. Micron's transition to replacement- gate provides better scalability with superior power and performance for several generations of 3D NAND to come. While floating gate was competitive across the key product attributes and made sense for less than 100 layers, replacement gate is the clear choice for greater than 100 layers. Despite the much higher layer count, our 176-layer replacement gate NAND has about the same Z-height as our current floating gate NAND in production and can easily scale to greater than 300 layers with dual stack technology due to the structural simplicity and better aspect ratio for critical etches in the replacement gate technology flow.
In addition to the superior cost we see with replacement- gate technology, it also delivers better power efficiency and performance, enabling us to better serve our diverse end markets from edge to cloud. We also see the replacement- gate technology being able to support improved QLC compatibility for future node transitions with superior endurance capability. Now turning to products. Today, I will highlight three leadership areas: ultra-bandwidth solutions, mobile, and solid-state drives. Memory and storage are foundational for artificial intelligence. Micron has strong product portfolios addressing this high-growth market, our ultra-bandwidth solutions are critical to resolve the data bottleneck that can be created while analyzing the massive data sets for AI. As I mentioned earlier, we have begun revenue shipments for HBM2E products, which are a clear enabler for training and inferencing in the cloud.
These products extend system bandwidth to greater than 2 TB/s and leverage our more than 20 years of experience in memory stacking and advanced packaging. This is an area where Micron has tremendous strength with thousands of patents. On the edge, our products play a critical role in inferencing. Our proprietary industry-leading GDDR6X product has applications for AI inferencing on the edge and for gaming. We're extremely excited with what we've been able to accomplish with our GDDR6X, which was developed in close partnership with NVIDIA. The partnership has enabled them to deliver superior end-user experience utilizing our industry-leading graphic DRAM bandwidth. This has allowed them to deliver differentiated system performance of greater than 1 TB/s . Our GDDR6X utilizes differentiated PAM4 multi-level signaling, which doubles the data transfer rate.
This GDDR6X also lowers the power consumption by approximately 20% relative to industry standard GDDR6, helping improve energy efficiency on platforms where it's used. Leveraging our low-power DRAM and NAND technology leadership, Micron has also emerged as a technology and product leader in the mobile space with a complete portfolio of mobile products that are qualified with all major chipsets. The breadth of our product portfolio offers our customers greater flexibility to design phones that better match their target market segments and redefine the end-user experience. Micron's LP5 is a great example of a product that redefines the end-user experience and our close collaboration with customers. Collaborating closely with Xiaomi, Micron was first to bring LP5 DRAM technology to market. This technology meets the growing consumer demand for 5G and AI functionality in smartphones.
Building on the success we've had with LP4, we lead in LP5 technology in power efficiency and speed. Our 1z- nanometer LP5 product has approximately 20% lower power consumption for bandwidth-intensive use cases, including 8K video recording compared to competitors' LP5. As mentioned before, we expect a further 15% improvement with our 1-alpha DRAM node. Our LP5 is also the fastest low-power DRAM in the market, delivering industry-leading gigabits per second, translating into better performance for AI applications, superior photo and video, and more. Micron has growing momentum across our expansive SSD portfolio. We have made significant progress over the past year and now have NVMe SSDs for data center, client, and automotive. We're leveraging greater levels of vertical integration to deliver differentiated solutions to our customers. Our broadening portfolio of SSDs using internally developed controllers is a great example.
Micron is an industry leader in QLC SSDs, providing leading density and performance at a compelling value to accelerate hard disk drive replacement. Micron's broad portfolio also delivers breakthrough performance on the other end of the spectrum with the world's fastest SSD. The X100, based on 3D XPoint and our proprietary system solution innovations, delivers close to 4x better random read and mixed workload bandwidth versus competitor SSDs with the same media. Our mission is to transform how the world uses information to enrich life for all.
This starts with our focus on innovation, technology acceleration, and execution. This focus over the past several years has resulted in the significant advancement in our overall competitive position. It extends to products where Micron has the industry's broadest portfolio and is driving to deliver product leadership. It also enables our customers to unleash the power of data and win in the data-centric era.
With that, I would like to thank you for your participation in today's webcast and open up the line for questions.
Thank you, sir. As a reminder, to ask a question, you will need to press star one on your telephone. To withdraw your question, please press the pound key. Please stand by while we compile the Q&A roster. I show our first question comes from the line of CJ Muse from Evercore. Please go ahead.
Yeah, good afternoon. Thank you for hosting the call. I guess, Scott, my question is on EUV. You talked about really a focus on cost. Just curious, what kind of improvement in throughput do you think you'll need versus ASML's D tool, to get to the point where it's cost competitive with multi-patterning? How do you think about the time to yield, and uniformity within that kind of economic bucket of when adoption of EUV would make sense for you guys? Thank you.
Sure. Thanks for the question. First off, without getting down to specific numbers, we've looked at the roadmap, including both performance and long-term performance in terms of long-term downtime on tools, as well as the overall just capability roadmap of EUV in the industry. There's clearly going to be different adoption times for different competitors depending on situation. For our particular applications on DRAM, we do still think it's going to be another two or three years before it makes the most sense for us to implement EUV based on assumptions that the performance will continue to make good progress and improvements over the next several years. I think the throughput roadmaps are kind of out there for different, or at least assumptions around them for what the supplier is going to provide.
We think that the roadmap will hit sometime in that time period, the right throughput for us to go forward. The second piece, in our decision, is really around making sure that the overall quality of our products can be maintained as we continue to shrink. Our confidence in our multi-patterning approach that we've talked about before is high. Our ability to execute high-quality products, as well as to develop them quickly is also high. I think we're confident in this approach. We think we'll be prepared to implement EUV at the right time for Micron and continue to keep our technology in a strong position, some of which I talked about today in terms of where our DRAM roadmap is at now, which is a strong competitive position, and we believe that will continue through the next several years.
We'll implement EUV at a time when it lets us continue that pace.
Thank you. I show our next question comes from the line of Harlan Sur from JPMorgan. Please go ahead.
Good afternoon. Thanks for hosting this event, Scott. We know what the team's cost-down targets in DRAM and NAND are going to be this fiscal year, down mid-single digits percentage in DRAM, down low to mid-teens percentage in NAND. But with the roadmap that you've just outlined for your future technologies, what can we expect in terms of DRAM and NAND cost-down targets on an annualized basis?
We're not changing our projection on what our cost-downs are going to be. Our strategy continues to be to optimize our technology nodes with the capability to get the most cost down that we can out of them, depending on how we move forward with the amount of bit growth we have each year. Our strategy continues to be aimed at matching our supply growth with where we see the demand growth being. Inside of that, we optimize our cost structure, and these technology nodes, both from the NAND and the DRAM side, really let us have an advantage or an opportunity to optimize that cost structure in a meaningful way, by providing a significant benefit.
Both the 1-alpha and the 176-layer nodes are better nodes than we've introduced on the prior generations. That happens through time as every node is not created equal, neither in the NAND side or the DRAM side. We tend to have some nodes that are a little better and some that are a little bit worse. These are both very strong nodes. Overall, we'll continue with the pace that I've talked about before.
Yep. Thank you.
Thank you. I show our next question comes from the line of Timothy Arcuri from UBS. Please go ahead.
Thanks a lot. I actually had two questions wrapped into one. I guess the first question on slide 13. It looks like for 1-alpha, you're sort of getting back to the same sort of bit per wafer growth that you had for 1X. I guess the first question is for Dave, and then the second question is for Scott. Dave, does this mean that the cost-downs should get back, if you look at 1z versus 1-alpha? Should the cost downs for 1-alpha get back to the mid-teens that they were for 1X versus the mid-singles today for 1z? I guess for Scott, clearly it's not related to EUV, so can you maybe double-click a little bit on how you're getting that increase in bit per wafer? Is it some aspect of 3D DRAM, something like that? Thanks.
Sure. Dave?
Yeah. Timothy, we don't talk about the specific cost declines by node. I would say, I think you're making a good assumption that at least directionally, that 1-alpha has a really good cost structure to it, that it contributes to actually decent cost declines for fiscal 2021. We talk about this mid-single digit, but that includes some mix headwinds. You strip that out, it's actually a bit higher, the cost declines. Of course, 1-alpha, doesn't really start getting going until the first half of the calendar year. That will certainly mean that, on average, that cost is much better than that, and is helping drive decent cost reduction to fiscal 2021 that should carry on in a more meaningful way, in fiscal 2022. That's about as much, kind of quantitative information that I can give you on the cost side.
On the architecture side, I would just say this is purely a shrink on planar DRAM, and the combination of how we've chosen to develop this node in terms of the minimum feature size, and as well as we have a substantial improvement on this particular node, purely from design efficiency. One of the challenges that we have had in the past node or two, in terms of driving the best possible bit per wafer, has been a need to improve our design efficiency. Our design team has really done an outstanding job here with what I referenced on 10% of the efficiency being purely just out of how we designed this chip, in a more efficient way, relative to the previous 1z node. The rest of it comes from just the technology shrink in standard planar DRAM.
Okay, awesome. Thank you for both of those.
Thank you. Our next question comes from the line of Joseph Moore from Morgan Stanley. Please go ahead.
Great, thank you. I wanted to ask about your lead in GDDR6X that you talked about. How long do you think you keep a strong position there? I guess when you talk about using PAM4 in a DRAM chip, that's not a capability that I would've thought Micron had until that chip came out. How long do you think it takes your competitors to get to where you are on that technology?
Sure. Well, first off, I think one of the important things about a development like this, where we're working closely with customers is that we're able to really enable some special products as we have, and some products that are incorporating and taking advantage of the technology that we've developed over a number of years. While I can't comment on how specifically long it's going to take any of our given competitors to develop something similar, I know that it gives us an opportunity to create differentiation for our customers, which is important. For sure, a DRAM development from ground up on a new technology takes a significant amount of time no matter what. Assuming people started trying to figure it out once we brought it out, then it'll take a year plus, but it can be longer.
It's I think a really novel technology advancement and we hope to have more of those in the future, partnering closely with our customers.
Very helpful. Thank you.
Thank you. Our next question comes from the line of Aaron Rakers from Wells Fargo. Please go ahead.
Yeah. Thanks for taking the question, and congrats on the strong execution. I guess my question's away from DRAM and NAND. I just wanted to ask about 3D XPoint as you continue to kind of carry 200 basis points plus of headwinds of gross margin. Any update on how we should think about the progression of 3D XPoint, the SSD roadmap, and when we should kind of consider that hitting a volume and kind of lessening that gross margin headwind? Thank you.
Yeah. I might leave that one for Dave on relative to the financial terms. We're focused on the technology. We continue to be in terms of creating differentiated products. We'll have more on that as we go through this year on exactly what those products are and what the specific, probably more clear estimates of the volumes are. At this point today, I can tell you we're making strong progress in the development of those products and we have confidence in the roadmap. Other than that, I'll leave that to Dave to add any color he'd like to.
Sure. On the underloading charges, we were, I think, at about $155 million in the third quarter. We managed to get that down, despite the extra week, down to about $135 million in the fourth quarter. It should trend through the year and I think by the end of the year, get fairly close to $100 million of underload charge. We are making some improvements while we wait for the products to ramp by just better managing the spend of that specific fab. As you, I think, point out, and as Scott talked about, really where we see these underloading charges really go away is when the volume of those products start to ramp in the fabs, and that gets the fab to be fully utilized and thus, those underutilization charges get de minimis.
It's going to take a while for that to happen, probably a couple of years. Whenever you're dealing with new technologies like this, even as fast as we can innovate, still the market takes a while to adopt these in volume and figure out use cases that really exploit the technology. We think that will take a few years before that really happens. We'll likely see a little bit of revenue in the next couple of years, but I think it'll be relatively small and then I think at some point we'll see a knee of the curve here and the products will take off and that underutilization charge will cease to be a headwind for us.
Thank you.
Thanks.
Thank you. Our next question comes from the line of John Pitzer from Credit Suisse. Please go ahead.
Hey, guys. Thanks for taking the question. Thanks for doing the technology roadmap. Scott, I'm just kind of curious, when you think about DRAM and the introduction of EUV, when you guys move to EUV, would you expect that to be kind of a normal shrink node for you or is it going to be something akin to replacement gate where you have to go through some learning pains before you kind of get normal cost downs? To the extent that EUV sounds mostly like a cost decision to you, not a capability decision, I'm just kind of curious as to why you think peers will be moving to EUV more quickly than you. What are they seeing on the cost side that you guys aren't?
Sure. Well, first off, I don't think it will be something comparable to replacement gate. I think it'll come in smoothly. We've had transitions of lithography before, we've managed them. I think that overall EUV, it will be a number of years that we're working on that by the time that we are implementing it into volume production. I think we'll be confident, it won't look like a step function of any sort. It'll be a normal cost reduction, normal technology roadmap. Effectively, the technology roadmap will be largely decided independent of EUV. It'll be based on what cost reductions we're targeting, what technology capability overall is at the time that we're bringing it in. Sorry, did I get your whole question there, John, or was there more to it?
No, you did. That's great. I'm just kind of curious as to the extent that EUV is a cost decision for you and not a capability decision, why do you think peers are moving more quickly than you guys are? What are they seeing on the cost side that you're not?
Of course, I can't speak for all of our peers. Certainly, there are different business models across the different peers with different both product mixes and quality requirements, and as well as other aspects of their business that may make it important for leveraging EUV across more than just DRAM. In the end, there's multiple reasons why competitors may choose to do that. I've said it many times, but we're very confident in this decision. We'll have it when it is beneficial, and we are putting a significant amount of effort into making sure that that timing is chosen correctly for optimizing our business.
Thank you.
Sure.
Thank you. Our next question comes from the line of Steven Fox from Fox Advisors. Please go ahead.
Thanks. Good afternoon. Hey, Scott, I was wondering if you can maybe dig in a little bit into some of your first comments around how you're integrating for tighter vertical integration going forward. How has that maybe driven some of the products you highlighted today in terms of the advancements and maybe how you see that playing out as more of a competitive advantage going forward? Thanks.
Sure. Thanks for the question. We have been focused on this over a couple of years here, and where it's really playing out right now is in our improvement, both in our engagement with our customers, and specifically in our focus on adding higher value products to our mix. I think I mentioned that on the NAND side, we've transitioned through a period of time here to having about 80% of our bits sold in higher value products.
Of course, there's a variety of different kinds of products, and our vertical integration focus is aimed at making sure both that we pull customer input back in as early to the development process as possible, but then also making sure that we have tight alignment between our end system product, subsystem product, engineering teams, all the way forward to the decisions we're making at silicon, and then solving problems in ways that
That enable us to pick the right place in the stack to solve the problem, whether it's in firmware, whether it's in core silicon technology, giving us really more options. Micron historically has pushed almost all of the solutions back into core silicon, it has not been a strength of ours, if I look back five years, for sure, or more. Our ability to solve things any way except in core silicon was very limited. We have made tremendous strides over the past two to three years in really making sure that we have the talent and the capability to make sure that we have internal controllers of high quality, that our firmware is excellent, and our ASIC teams are strong.
I think that just more tools in the box for how we go develop and deliver product solutions is something that you're starting to see now, and I think you'll see more over the next few years.
Great. That's really helpful. Thank you.
Thank you. I'll share our next question, comes from the line of Mehdi Hosseini from SIG. Please go ahead.
Yes, sir. Can you hear me?
Yep.
Yes.
Sure.
Okay, sorry. I had a problem with the mute button. Most of my questions have been answered. Just have one follow-up regarding high memory bandwidth. When do you think this is going to be actually material to Micron? I'm asking because there are technologies around it that are evolving, going to production early 2021. In that context, are we at the verge of inflection point for an R&D turning into meaningful revenues?
I'll start and then maybe Dave wants to add something to that. I think you're familiar with history here on several fronts on the product side for us. We went down the Hybrid Memory Cube path and developed a lot of this technology and capability earlier, and then shifted to align with the rest of the industry on HBM technology just over the last couple of years. This first node of ours is not going to be huge volume. I think it's still probably, Dave will comment, will be material, but at a pretty low level. Our objective here really is to build on this first node of HBM2E and turn this into an opportunity for a real material impact to our business with HBM3E and beyond that. I'll let Dave add any commentary to that.
I think you answered it right, Scott. Obviously, we have a roadmap for HBM. The earlier versions take some time to kind of seed the market. The expectation is that as we roll out additional products, we'll see a higher percentage of revenue coming from this. Again, in these product portfolio type businesses, the idea is to offer a number of different solutions like GDDR6 and GDDR6X, that kind of achieve what the customers are trying to get optimally from their solutions. The idea is to provide a complete suite of products to be able to do that.
Great. Just one follow-up for Scott, going back to your SSD portfolio, you highlighted and compared Micron's QLC performance to competitors. Is this a function of just the NAND device itself, or the controller used, or a mix of different vectors? If you can elaborate, it'll be great.
Sure. It's a mix of different vectors. I think we've put significant focus into how to build QLC-based solid-state drives. Certainly, our NAND experience has been one of learning how to make QLC that is effective for solid-state drives. We have put a substantial amount of effort into how those drives overall are put together from the other vectors as well.
When you say drive, is this still targeting mission-critical, or are you actually referring to cold storage?
For sure, we're targeting to be able to continue to push our QLC-based drives to take bigger and bigger parts out of the hard disk drive space.
Not any particular segment of the HDD market?
Cold storage, for sure. The markets that we're in now, pushing on enterprise and different aspects of where we can put QLC drives into, those continue to be the same vectors we've talked about before. I think the expansion in the future is to how much more at the points of price and performance we can provide products that give us the opportunity to take more and more out of the hard disk space is a substantial growth opportunity.
Got it. Thank you. Thanks for the details.
Sure.
Thank you. Our last question comes from the line of Karl Ackerman from Cowen. Please go ahead.
Good afternoon. Hey, Scott, you spoke of the differences between floating gate and replacement gate above 100 layers. How much of your decision to transition to replacement gate is due to the fact that less than 10% of industry bits are on floating gate today, and there seems to be little innovation on floating gate from equipment companies? I guess given your recent consolidation in the NAND flash space, how do you view your competitive position as competitor plans to stay on floating gate for two to three more generations? Thank you.
Well, I think we spent some time talking about why we made the decision back then. I think all of the reasons that we pointed out back then for replacement gate going forward are still valid. One of the reasons in the list certainly was the focus from the key equipment suppliers aimed at replacement gate type technology and being able to take advantage of where the equipment industry's funding is. From our primary point of view was more around our belief both that the floating gate technology really doesn't have a roadmap to provide cost reduction beyond a certain point. The second piece is really fundamentally around performance capability. Once you get up above a certain density, specifically in mobile applications and in other high-performance drives that are important to our markets going forward, they're much better supported on the scaling roadmap with replacement gate technology.
Thank you. Ladies and gentlemen, this concludes our Q&A session and today's conference call. Thank you for participating. You may all disconnect.