Analyst & Investor Webcast

May 23, 2019

Slides

Good afternoon. My name is Daniel and I will be your conference facilitator today. At this time, I would like to welcome everyone to Micron's event providing for Executive Vice President of Technology Development, Scott Deboer, to present a technology roadmap and strategy. Call. You. Thank you. It is now my pleasure to turn the floor over to your host, Farhan Imma, Head of Investor Relations for Micron. You may begin your conference. Thank you. Good afternoon and thank you for joining our update call of technology roadmap On the call with me today is Kottipur, Executive Vice President and our CTO. Our call today will be focused on discussion regarding our technology roadmap and there will be a Q and A session at the end, during which our CFO, Dave Simpson, will also join. A webcast replay of this call will be available on our website later today. As a reminder, the matters we will be discussing today include forward looking statements. These forward looking statements are subject to risks and uncertainties that may cause actual results to differ materially from the statements made today. We refer you to the documents we filed with the SEC specifically our most recent Form 10K and Form 10Q for a discussion of risks that may affect our future results. Although we believe that the expectations reflected in the forward looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements. We are under no duty to update any of the forward looking statements after today's date to conform these statements to actual results. I'll now turn the call over to Scott. Good afternoon. I'm Scott Deboer, Executive Vice President Technology Development at Micron Technology. I'd like to welcome you to this webcast where I'll focus on how we are accelerating memory and storage innovation at Micron. Today, I'm going to provide some updates on our key technologies relative to Strong focus at Micron on our team on our core technology innovation and on improving our execution continued to lead to a strengthening of our overall competitive position. I'll start off today with an update on the team and the resources we have focused on delivering the core technology for the company. We're very proud of our talented technology team working on developing the technology and products that will drive our company in the future. We're confident that our global talent is a significant competitive advantage fueling our innovation. Recognition is a top 50 company in terms of U. S. Patents as well as being recognized as a Our focus on getting even stronger is underpinned by our ability The education credentials and industry experience of a people we're hiring are indicators of our focus on raising the bar. And our recognition as a great place to work helps us attract new talent to Micron. In addition to our focus on the talented current team at Micron, we're reaching back support of the pipeline required for STEM Education, both in K-twelve and in universities and close engagement with top global universities. On the diversity front, I'm also pleased to note that of the students participating in the fiscal year 'eighteen R and D internship programs, approximately 50% were women. We continue to strengthen our core R and D capability in Boise, both with key talent and infrastructure additions. Our team in Boise focuses on early technology investigations for our core memory products as well as more disruptive technologies. In addition, we've enhanced our R and D efforts directly at the manufacturing sites by adding both talent and infrastructure to support more rapid execution on future technology delivery. Our global R and D model is optimized to efficiently execute on disruptive technology, while at the same time ensuring we have sufficient capability directly inside the manufacturing facilities to deliver world leading technology qualifications and yield ramps. This 2 pronged approach to technology development not only allows us to perform different stages of development programs in the most efficient and flexible environments, but it also allows Micron to uniquely take advantage of our diverse global talent base. This global technology team and the resources they drive are focusing on delivering differentiated technology that supports our business across a broad spectrum of different customers wants and needs. Power, performance, density, latency and differentiation in our products is greater today than ever before. Whether it's DRAM, NAND, 3 cross point or other new emerging memory technologies, Our team is focused on delivering unique capabilities for our customers. Our rich portfolio products and solutions address critical needs of our customers. Whether it's power, form factor, performance, reliability or another attribute, we're meeting the challenge as we work with our customers across spectrum of markets shown on this slide to design memory and storage solutions that continue to deliver. On specific future technologies we're collaborating with our customers to bring to market. We continue to have the industry's most comprehensive technology portfolio powered by the global talent and infrastructure I've described on the previous slides. Today in the time I have available, I'm going to provide an update progress since last year's analyst meeting specifically on our NAND and DRAM Technologies. At our analyst meeting last year, I focused on our competitive progress over previous 5 years. As you'll remember, we'd improved from a position in 2013 where our leading technology was roughly half gigabytes per wafer as compared to the most advanced competitor to a substantially better competitive position in 2018 of approximately 10% to 15% off from the leader. Our progress continues as I'll show in the next couple slides. Our team remains laser focused on narrowing any technology capability gap with a best in class This year, we're introducing the industry's first LP DDR4 16 gig monodize solution on our 1Z nanometer technology. Customer qualifications are currently in progress for this leading edge mobile memory product. We're currently in the middle of our yield ramp on the 1Z technology I'm pleased with the progress improving the cost as well as the product performance that is ultimately provided by this technology. Some examples shown in this slide include important power metrics for DRAM performance in mobile devices running common applications, like playing music and watching YouTube videos. As illustrated, we've delivered excellent power performance relative to our competition with our 1Z nodes similar to what we accomplished on our 1X and our 1Y nodes. We will continue the trend of improving our competitive position with the 1Z node ramp, but we recognize we still have a ways to go as we will continue to focus on cost and performance leadership. Overall, when looking at the industry trends on this slide, DRM scaling is clearly slowing as the technical challenges are leading to reduced levels of improvement on successive nodes, both in terms of bits per wafer improvement and cost per gigabit reductions. As the CapEx intensity related to scaling continues to grow, the cost of scaling. While the trends toward less bit growth per node and less cost reduction per node are very clear, and certainly will not see the types of no to no improvements in the future that occurred historically. Our team remains focused on the difficult task of delivering future nodes that provide viable returns. We believe that our combination of global talent and extensive DRAM experience position Micron uniquely with the capability to identify innovative ways to deliver viable future technology nodes despite the obstacles in front of us. As we look at the DRAM technology roadmap, we're currently focused on 4 nodes in various stages of development. Looking beyond our 1 beta node, our focus is on identifying a viable solution given the difficult physics and cost challenge the node presents. I'll discuss more on this on the next couple of slides, but lithography is not a fundamental DRAM scaling limitation. Micron's pattern multiplication technology is a strategic advantage and it's one that we intend to continue to leverage for the next few DRAM nodes. The relative cost structure of multi patterning technology versus EUV is shown in the graph on the slide as a function of future DRAM nodes. The technology was first introduced by Micron, and we continue to advance the cost structure and technical capability of multi patterning lithography over time. Based on the development work we have already completed, we're confident in the technology capability and cost efficiency of our multi patterning approach for the 1Z node through our 1 gamma node. That said, we have an ongoing evaluation of EUV lithography for DRAM to ensure that we're prepared in the event the technology capability improves to the point where it aligns well with our roadmap. We will be prepared for implementation of EUV if and when EUV performance can be beneficial to Micron. As just mentioned, we're continuously looking at EUV as an option for DRAM. On this chart, you see an assessment for advanced DRAM nodes. While EV can certainly be viable in terms of process capability for certain levels on the 1Z and 1 Alpha nodes, Our proprietary multi patterning technology still significantly outperforms the EUV exposure options in terms of cost structure for these nodes. For more advanced nodes, EV can approach overall cost parity at very low exposure doses but under these conditions, the pattern quality is not acceptable. Alternatively, if very high exposure doses processing is used, The pattern quality can be improved to be potentially usable. However, in this case, the cost is substantially higher than the multi patterning alternative. Considering these factors, we're not planning on implementing EUV in the near future, but we'll continue to look at the best interception point as the technology advances. Similar to DRAM, I discussed our competitive NAND progress at the Analyst Meeting last year. As you'll remember, We improved from a position in 2013 where our leading technology was roughly 60% of the gigabits per wafer as compared to our most advanced competitor to a position of competitive leadership Our continued progress over the past year providing Our overall strategy involved first establishing a replacement gate pilot line at lower layer counts for yield and reliability learning ahead of the 128 layer ramp. Our success enabling the replacement gate NAND yield utilizing this pilot line has greatly increased our confidence and experience as it relates executing on the 128 layer node on a competitive timeline. As a reminder, our RG technology is a unique combination our industry leading CMOS This combination which are all key attributes per wafer and limit the cost reduction pace over the next few years. No increases that we're seeing in gigabits per wafer, driven by the planar to 3 d conversion. Gigabits per wafer growth slows beyond 64 layer transition as the industry will be focusing on more traditional conversion from one three d node to the next. As opposed to a planar to 3 d transition that we saw in the past. As shown in the graphic on this slide, the cost reduction per node is leveled off over the past few years as a direct result of the CapEx intensity and process complexity. Roadmap development is in progress for beyond partial portfolio node for Micron and will be followed by a 1y y layer node that will cover our full product portfolio. We believe we will be very well positioned to drive cost and performance leadership as we emerge from the floating gate replacement gate transition and focus on delivering The new Micron is about driving our performance to still a higher level and of course, continually challenging ourselves to improve our operational execution is a key aspect of this. I'm going a time to benchmark levels and beyond has been a major focus of our development and manufacturing teams. As illustrated on this slide, we have made major improvements over the past few years in our yield ramp execution reducing our time to mature yield by more than half for both DRAM and NAND. The significance of this execution improvement is magnified considering the increased complexity and difficulty in scaling we're facing along with the rest of the industry. It is a result the Micron team is very proud of. Our focus on innovation, technology acceleration execution over the past several years have resulted in significant advancement in our overall competitive technology position. As I said a year ago and still believe today, Micron is in a stronger position in terms of core technology capabilities than at any time in the past 25 years. That, I'd like to thank you all for your participation in today's webcast and open up the line for questions. For questions. Our first question comes from Kevin Cassidy with Stifel. Your line is now open. On the, maybe persistent memory is a topic of conversation for a lot of AI applications and data center, is 3d Crosspoint your solution for that? Or do you have some other products in development that would fall into the category of persistence memory? Yes. Good question. We have, we have, certainly 3 d cross point as as one of our solutions in that application space. We have other products, under development with different emerging memories. In addition on some of the applications can be met a combination of standard year end demand. So, like paper persistence from the NAND. Okay. And just on the, maybe on the cost side of the development, do you get leverage with 3 d cost point, with the NAND and DRAM, is there enough enough similarity there that you're being able to use some of the development you've had for NAND for the 3 d cross point? There's some similarity, but as probably you're aware, we actually have been working on 3 d cost point for a very long time. And, so while there's some tool set similarity, the technology actually is quite different. So the expertise in NAND or the work that we did on NAND doesn't add that much to the ability to through to Crosspoint. But it's still been a very long development process that we started many years ago with Midtown. And our next question comes from Mehdi Hosseini with SIG. Your line is now open. Yes. Thanks for taking my question. First one, Scott, you mentioned some data points on EUV. I'm just curious, is that based on the AUB 3400 B? And if so, When should we hear from you results of your R and D on the seat version given the fact that ASML has talked about significant improvement and are we going to wait for next year for the same update or we should be able to come back and give us an update? And I have a follow-up. Yes, fair question, Mehdi. Just to be to be clear, our evaluation on EV and our assessment is actually based on the full roadmap of EV, not just the 3300 B. If you look at pattern technology, potentially why you asked the question that the 3300 B from a resolution point is very similar to the next couple of tools, but the the roadmap that we look at when we're making an assessment on where the intercept point is, is based on the throughputs and the capabilities of the latest tools. A follow-up question too, right? Yes. A quick follow-up. As you change the NAND underlying technology, is there any IP royalty commitment to a third party that we should be thinking of? No. Have a strong IP position on our NAND technology, with more than 40,000 patent historically, and we're very comfortable and well positioned with our IP related to NAND technology. Great. Thank you. Thank you. And our next question comes from Rajvindra Gill with Needham And Company. Your line is now open. Yes. Thank you for taking my questions. You mentioned the transition from 2 d to 3 d generated a significant amount of bid growth. But now that the transition is over and we're going now into kind of normal iterations within three d that the note to note transitions will slow down a bit. I was wondering if you could kind of talk a little bit about that in further detail. How much will it slow down per node and the correlating cost reduction? How does that level off as well per node? Thank you. Well, I can talk about kind of the near term and maybe just generally where we see the industry. But overall, the cost reductions going forward, as I showed, have been pretty flat over the past few years. And I think NAND just like DRAM is going to be a pretty significant challenge for the industry to hold those kind of cost reductions even level. So likely they'll continue to come down some. If you look at just a 3 d technology, when you go from through these first few nodes, you go from 32 tiers for us to 64 tiers where we're basically doubling the bids. It's a substantial improvement. When we're up in the hundreds of tiers and we're looking at what the percentage increase in it is on our next nodes as an industry. The percentage increase is going to be is going to be less. If you just look at us going from 96 tiers to this next node that we talked about today, 128, it's just the math of the bid increases in the same area or lower. And when we were coming from Planner, the increases were very substantial when we're coming from a 15 or 16 nanometer planar flow up to a 64. The fit increase on the wafer was massive. The cost and the number of wafers that fit in a given amount of fab space was offsetting the amount of bit growth, but obviously the historical bit growth was big during that transition. And for my follow-up, the 128, what are the kind of the first application that you see, consuming 128 layer? How are you going to position this by end market? Thank you. Sure. Our end markets generally aren't going to change substantially. We have mobile products, we have SSD product, and we'll be working with our customers to find the best fits on those. But I wouldn't look at a big change there. Thank you. Our next question comes from Aaron Rakers with Wells Fargo. Your line is now open. Yes. Thanks for taking the questions and also doing the call today. Yes, I want to build on that last kind of comment. I think last quarter or even the quarter before the commentary around moving to 128 with replacement gate would be kind of a bit of a challenge from a cost down perspective. So I'm curious, first of all, how do I think about that? And I think you even alluded to the fact that there would be fairly limited implementation of that process node across your product portfolio? And kind of building on that, how do we think about the progression from there to the 1 YY process node using replacement gate. How do you expect to shorten that cycle? I mean, just trying to understand of how long maybe you might be a little bit cost disadvantage for that first implementation of replacement kit? Sure. That's a good question. There's several pieces to that. And as you mentioned, we've said before that our 128 tier node, isn't going to provide the same kind of cost advantage. Part of that is we're coming from a 96 tier node on FG that was really exceptional from a cost point of view. So when we go to our 128 tier note and talk about the benefit not being as substantial through this period of time, it's really not that we're stating our year note is going to be substantially worse than, than our competitors. It's really that we were coming from a strong spot and we have a big capital, a change out and involved with switching from FG to RG. So we think our part will be competitive on 28 tiers. It just won't be the kind of cost reduction we've seen node to node previously. So think maybe half what we've gotten on previous notes. When we go beyond that, we will be focused on trying to have a an industry competitive cost reduction relative to kind of what we're projecting here on those beyond that. We'll have the technology in place that mature yield on a previous note and it will it'll have a commonality in the tool sets substantially better and let us drive a good cost reduction path. Okay, fair enough. And then just as a quick follow-up, I'm curious, some of the things you talked a lot about kind of the technology itself down to the chip level. But I'm curious, I mean, from a roadmap perspective, from a product perspective, are there things on the NAND flash side, be it NVMe Enterprise SSDs or even the commercialization of 3 d cross point? Any changes in the roadmap for those those solutions? Thank you. Well, certainly, as we've mentioned, both today and previously, we are thinking of the 128 tier node is not a full portfolio node. So in terms of changes, there won't be big changes on the 128 tier node. When we look farther out and we ran we round out our whole portfolio, we'll be in a solid position on the next node with a full portfolio. And at that point, certainly we'll have, 3 d XPoint products out in the market and we'll have other opportunities in terms of NVMe and other things. And we're not announcing any of those today, but full, all those things will be in play by the 2nd generation of replacement gate for us. Thank you. Our next question comes from CJ Muse with Evercore. Your line is now open. Great. Thanks for taking the question. And Scott, thank you for doing this today. I guess the first question, I think on the 3 d crosspoint side, we've been so focused on the data center server opportunity. And less folks elsewhere. And I guess now that we have time with you, we'd love to hear what those opportunities are outside of the server market. And what the timeline looks like for a ramp in those areas. We're not announcing any new products on that today. We've talked in the past that we do see opportunities for 3 d XPoint in mobile, in data center in a variety of different applications, and we think those applications will continue to expand. But no new ones to talk about today, but we're absolutely focused on product creation and generating value out of this unique technology that Micron and Intel have created, and being in a position over the next couple of years where that becomes more a substantial part of our business. Okay. Thanks. And I guess as a follow-up, I think Dave's on the line as well. I'm curious if you can comment at all on Huawei in terms of your exposure there, impacted the revenues whether your inventory, I presume largely on the handset EMCP side, whether that's fungible, and I guess any other color around that embargo that you can offer? Thank you. Yes, sure. So, yeah, obviously, Thursday kind of evening, we were restricted from exporting additional product to Huawei There was some expectation of a special license that was that would be granted that did come out on Monday. However, the license was really specific to supporting products already installed or cell phones that are already sold. So really, that's a minimal impact to us one way or the other. So we are not shipping to Huawei as of, Thursday evening. They, if you have looked at the 10 Qs of the first quarter 2nd quarter, they represented 13% of our revenue for those two quarters. So obviously, they're a meaningful customer. And so, obviously, that will have a financial impact. Which we will update you on, at the earnings call. So we don't intend to update anything related to that right now. At this point, we're obviously hoping for a quick resolution on it. But in the meantime, focused on the rest of the customer base, which of course needs to be supported and serviced. And And also on all the initiatives that we've got going on, like Scott's talked about around technology and cost and improving our mix. And all the while, I would say just really focused on managing the company in a disciplined fashion financially. So, again, we're hopeful for a quick resolution of this, but we don't know much more than I think than anyone else does And so we'll just have to wait and see how it goes. Excellent. Thank you. Our next question comes from pradeep Rahmani with UBS. Your line is now open. Thank you for letting me ask a question. I'm asking on behalf of Tim Arcuri. Scott, so, I get it that you're kind of saying that no EUV in the near term, but you're also kind of exploring it, as you go along. In terms of making a decision, ultimately, to go to EUV, on a future note. How much in advance do you think, you will know whether you have to go to EUV or not on a future note? Well, one of the benefits that I talked about last year about how we've set up our our development processes. We are looking a lot farther out in the future right now and doing a lot more. Early development on nodes to prepare, which is part of what's helped us improve our competitive position so much over the past few years. So I think we have plenty of runway to figure out, for a given node, at least 2, 3 years ahead of time when we would want it in volume manufacturing, for a variety of reasons we're very confident in the next few years. And I think, our confidence also goes to the fact that we're closely engaged and working on UV Technology and making sure that we have that runway we're going to need it. For the next several years, the multi pattern technology is just such a clear winner in our business strategy that we're in good shape and we'll keep watching it. Okay. And for a quick follow-up on NAND, beyond, I guess, the 128 layer, you still looking at, stacking or are you, are you considering, non stack versions as well? Well, that's we're not going to talk about technical details. We've been running STACK NAND technology successfully for multiple generations already. Today, I told you we're going to do it on 128. It clearly is a direction for extending technology into the future, exactly how we build the 1YY and beyond. We'll talk more about that as we get a little closer to it. And our final question comes from David Wong with Instinet. Your line is now open. Thanks very much. As you go to the 128 layer node on NAND and then to the 1Y and 2XX, what happens to your wafer cycle time through a fab? Did it go up, down or remain unchanged? That's a good question. There's a little bit of, circular argument. Discussion, I'll give you on that. Part there remains exactly the same. The overall cycle time depends on would naturally want to go up because of the just fundamentally, the increased layer count is more films, more, complexity on the wafer. But at the same time, we are working with all of our key suppliers to make sure that we we have the right solutions to minimize the amount of time increases or reduce the amount of cycle time in some of the steps. So our focus is clearly to minimize the amount of, of, cycle time increase as we go node to node. We do that through both. Working with our suppliers and also through, innovative approaches in changing exactly how we build the NAND, to try to make sure that it's as efficient as possible. It'll go up some, but we're definitely focused overall on mitigating that to every extent possible Great. And my follow-up, on DRAM, you've described several few generations and it sounds like they all got to have to do with language scaling. Are you looking at any alternative future nodes that have something more exotic than straight line with scaling in the same in the way that NAND moved away from scaling into 3 d. Is there any are there any other options for DRAM? DRAM is pretty complex in terms of there's not an obvious solution like unmanned where you just flipped it on its side and built it. So we're investigating lots of ways to build DRAM more efficiently in the future. And, just like we've talked about before, we're investigating different kinds of memory technology. So there's aspects that we're certainly looking at and we feel like we have some interesting things that we've talked a little bit about at Investor Days before relative to emerging memory and kind of the applications that can fit into. But we're not talking about any specific new DRAM architecture today. And this concludes our question and answer session. Ladies and gentlemen, thank you for participating in today's conference. This does conclude today's program and you may all disconnect. Everyone, have a wonderful day.